AS7C332MNTD18A sram equivalent, 3.3v 2m x 18 pipelined sram.
* Organization: 2,097,152 words × 18 bits
* NTD™ architecture for efficient bus operation
* Fast clock speeds to 200 MHz
* Fast clock to data access: 3.2/.
requiring random access or read-modify-write operations. NTD™ devices use the memory bus more efficiently by introducing.
The AS7C332MNTD18A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory (SRAM) organized as 2,097,152 words × 18 bits and incorporates a LATE LATE Write. This variation of the 32Mb synchronous SRAM uses the No Turnaround .
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