AS7C33256NTF18B sram equivalent, 3.3v 256k x 18 flowthrough synchronous sram.
*
*
*
*
*
*
*
* Organization: 262,144 words × 18 bits NTD™ architecture for efficient bus operation Fast clock to data access: 7.5/8.0/10..
requiring random access or read-modify-write operations. NTD™ devices use the memory bus more efficiently by introducing.
The AS7C33256NTF18B family is a high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) organized as 262,144 words × 18 bits and incorporates a LATE Write. This variation of the 4Mb+ synchronous SRAM uses the No Turnaround Delay (.
Image gallery
TAGS
Manufacturer
Related datasheet
Download (Size : 472.48KB)