AS7C33128PFD18B sram equivalent, 3.3v 128k x 18 pipeline burst synchronous sram.
* Organization: 131,072 words × 18 bits
* Fast clock speeds to 200 MHz
* Fast clock to data access: 3.0/3.5/4.0 ns
* Fast OE access time: 3.0/3.5/4.0 ns <.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable.
The AS7C33128PFD18B is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM) devices organized as 131,072 words × 18 bits and incorporate a pipeline for highest frequency on any given technology. Timing for this device is comp.
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