AS7C33256NTD16A sram equivalent, 3.3v 256k x 16/18 sram.
* Organization: 262,144 words × 16 or 18 bits
* NTD™1 architecture for efficient bus operation
* Fast clock speeds to 166 MHz in LVTTL/LVCMOS
* Fast clock.
requiring random access or Read-ModifyWrite operations.
NTD devices use the memory bus more efficiently by introducing a.
The AS7C33256NTD16A/18A family is a high performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) organized as 262,144 words × 16 or 18 bits and incorporates a LATE LATE Write.
This variation of the 4Mb sychronous SRAM uses the No Turna.
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