| Part number | AS7C1026C |
|---|---|
| Datasheet | AS7C1026C-AllianceSemiconductor.pdf |
| File Size | 287.41 KB |
| Manufacturer | Alliance Semiconductor |
| Description | 5V 64K x 16 CMOS SRAM |
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A write cycle is acplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
| Brand Logo | Part Number | Description | Other Manufacturers |
|---|---|---|---|
 |
AS7C1026A | 5V/3.3V 64K X 16 CMOS SRAM | Alliance Semiconductor Corporation |
See all Alliance Semiconductor datasheets
| Part Number | Description |
|---|---|
| AS7C1026 | 5V/3.3V 64K x 16 CMOS SRAM |
| AS7C1026B | 5V 64K x 16 CMOS SRAM |
| AS7C1024 | 5V/3.3V 128K × 8 CMOS SRAM |
| AS7C1024A | 5V/3.3V 128K x 8 CMOS SRAM |
| AS7C1025 | 5V/3.3V 128K x 8 CMOS SRAM |
| AS7C164 | 5V 8K X 8 CMOS SRAM |
| AS7C164A | 8K x 8 BIT HIGH SPEED CMOS SRAM |
| AS7C256 | 5V/3.3V 32K x 8 CMOS SRAM |
| AS7C256A | 5V 32K x 8 CMOS SRAM |
| AS7C256B | 5V 32K x 8 CMOS SRAM |
