Datasheet Summary
September 2006 A
®
5 V 64K X 16 CMOS SRAM
- Industrial (-40o to 85oC) temperature
- Organization: 65,536 words × 16 bits
- Center power and ground pins for low noise
- High speed
- 15 ns address access time
- 6 ns output enable access time
- Low power consumption via chip deselect
- Easy memory expansion with CE, OE inputs
- TTL-patible, three-state I/O
- Upper and Lower byte pin
Features
- JEDEC standard packaging
- ESD protection > _ 2000 volts
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
Pin arrangement
44-Pin SOJ (400 mil), TSOP 2
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21...
