AS4C512M16D3LA - 8Gbit DDR3L SDRAM

Alliance Semiconductor

AS4C512M16D3LA Datasheet Preview — Preview of AS4C512M16D3LA PDF

Datasheet Details

Part number	AS4C512M16D3LA
Manufacturer	Alliance Semiconductor
File Size	1.92 MB
Description	8Gbit DDR3L SDRAM
Datasheet	AS4C512M16D3LA-AllianceSemiconductor.pdf

AS4C512M16D3LA Product details

Description

Pin CK, CK CKE CS ODT RAS, CAS, WE DM BA0 - BA2 A0 - A15 A10 / AP A12 / BC RESET DQ DQSL, DQSL DQSU, DQSU NC Type Input Input Input Input Input Input Input Input Input Input Input Input/ Output Input/ Output Function Clock : CK and CK are differential clock inputs.All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK.Output (read) data is referenced to the crossings of CK and CK Clock Enable : CKE HIGH activates, and CKE Low dea

Features

- Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipe- lined architecture - Bi-directional differential data strobe (DQS and DQS) is transmitted/ received with data for capturing data at the receiver - DQS is edge-aligned with data for READs; center-aligned with data for WRITEs - Differential clock inputs (CK and CK) - DLL aligns DQ and DQS transitions with CK transitions - Commands entered on each positive CK e.

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Published: Aug 7, 2019 |