AS4C512M16D3LA
Key Features
- Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipe
- Bi-directional differential data strobe (DQS and DQS) is transmitted/
- DQS is edge-aligned with data for READs; center-aligned with data
- Data mask (DM) for write data - Posted CAS by programmable additive latency for better mand
- On-Die Termination (ODT) for better signal quality
- Synchronous ODT - Dynamic ODT - Asynchronous ODT
- Product part No
- Speed Grade Information
