UT8SP2M48 ssram equivalent, 96megabit pipelined ssram.
Synchronous SRAM organized as 2Meg words x 48bit Continuous Data Transfer (CDT) architecture eliminates
wait states between read and write operations Supports 40MHz.
Chip Enable 0, Input, Active LOW: Sampled on the rising edge of CLK. Used in conjunction with CS1 and CS2 to select or deselect the device.
Chip Enable 1 Input, Active HIGH: Sampled on the rising edge of CLK. Used in conjunction with CS0 and CS2 to s.
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