UT8SF2M40 Datasheet, Aeroflex Circuit Technology

 Synchronous SRAM organized as 2Meg words x 40bit  Continuous Data Transfer (CDT) architecture eliminates wait states between read and write operations  Supports 40MHz.

Chip Enable 0, Input, Active LOW: Sampled on the rising edge of CLK. Used in conjunction with CS1 and CS2 to select or deselect the device. Chip Enable 1 Input, Active HIGH: Sampled on the rising edge of CLK. Used in conjunction with CS0 and CS2 to s.