TSPC603R Description
The PID7t-603e implementation of the PowerPC 603e (renamed after the 603R) is a low-power implementation of the Reduced Instruction Set puter (RISC) microprocessor PowerPC family. The 603R is pin-to-pin patible with the PowerPC 603e and 603P in a Cerquad package. The 603R implements 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.
TSPC603R Key Features
- 7.4 SPECint95, 6.1 SPECfp95 at 300 MHz (Estimated)
- PD Typically = 3.5W (266 MHz), Full Operating Conditions
- Branch Folding
- 64-bit Data Bus (32-bit Data Bus Option)
- 4-Gbytes Direct Addressing Range
- Pipelined Single/Double Precision Float Unit
- IEEE 754 patible FPU
- IEEE P 1149-1 Test Mode (JTAG/C0P)
- fINT Max = 300 MHz
- fBUS Max = 75 MHz