Description
..
power implementations of the PowerPC Reduced Instruction Set Computer (RISC) architecture..
volts CMOS process technology and maintains full interface compatibility with TTL devices..
Features
- a dedicated L2 cache interface with on.
- chip L2 tags. Both are software and bus.
- compatible with the PowerPC603 and PowerPC604 families, and are fully JTAG compliant. The TSPC740A microprocessor is pin compatible with the TSPC603e family. G suffix
CBGA255 and CBGA360
Ceramic Ball Grid Array
MAIN.
