A48P4616 dram equivalent, 16m x 16 bit ddr dram.
CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 (5T) 166 200 DDR333 (6K) 133 166 DQS is edge-aligned with data for reads and is cen.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pin.
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