A48P3616B
Overview
The 128Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.
- Double data rate architecture: two data transfers per clock cycle.
- Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
- DQS is edge-aligned with data for reads and is centeraligned with data for writes.
- Differential clock inputs (CK and CK )
- Four internal banks for concurrent operation.
- Data mask (DM) for write data.
- DLL aligns DQ and DQS transitions with CK transitions.
- Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS.
- Burst lengths: 2, 4, or 8
- CAS Latency: 2/2.5/3
