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A48P3616B - 8M x 16-Bit DDR DRAM

Description

The 128Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation.

The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.

Features

  • CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 (5) 133 166 200.
  • Double data rate architecture: two data transfers per clock cycle.
  • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
  • DQS is edge-aligned with data for reads and is centeraligned with data for writes.
  • Differential clock inputs (CK and CK ).
  • Four internal banks for concurrent op.

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Datasheet Details

Part number A48P3616B
Manufacturer AMIC
File Size 1.45 MB
Description 8M x 16-Bit DDR DRAM
Datasheet download datasheet A48P3616B Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Document Title 8M X 16 Bit DDR DRAM Revision History Rev. No. History 1.0 Initial issue A48P3616B 8M X 16 Bit DDR DRAM Issue Date January 2, 2014 Remark Final (January, 2014, Version 1.0) AMIC Technology, Corp. A48P3616B 8M X 16 Bit DDR DRAM Features CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 (5) 133 166 200 „ Double data rate architecture: two data transfers per clock cycle. „ Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver. „ DQS is edge-aligned with data for reads and is centeraligned with data for writes. „ Differential clock inputs (CK and CK ) „ Four internal banks for concurrent operation. „ Data mask (DM) for write data.
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