1 Period Period selection input
2 GND Ground
3 Output Output control pulse
4 Contr. Control input
5, 6 Osc. Quartz-oscillator input
7 Test Test logic input/output
8 VS Supply voltage
4 5 Osc.
Figure 2. Pinning
Pin 1, Period Selection Logic
Period selection at Pin 1 is as follows:
Pin 1 = open,
st = 36
Pin 1 = ground
Pin 1 = VS (Pin 8), t = 60 s
Pin 2, Ground
Pin 3, Output Stage
Output stage, being short circuit protected is limited to a
current value of typical 150 mA. Apart from it, there is a
wvoltage limitation which controls the power stage at the
rate of V3 28.8 to 32 V and serves as an active Z-diode.
Output pulse width is 31.25 ms when quartz frequency is
32.768 kHz. It is independent of the selected period.
Pin 4, Control Logic
D Counting delay is typ 1.5 s (maximum 8 s) when Pin 4
is open and VS is switched on.
yD Programmable residual divider t 1 s is reseated if
Pin 4 is connected to Pin 8. This results in an absolute
vtolerance, at the start across “Reset/End” to be 1 s.
D Clock input to the 27 divider is inhibited, if Pin 4 is
vconnected to the ground (Pin 2). Absolute tolerance
for every interruption is 0.488 ms.
ăD An interruption is ignored (Pin 4 = ) during the out-
put pulse time.
*D When Pin 4 is switched to VS during the output pulse
time this output pulse will be reseated.
Pin 5, 6 Quartz-Oscillator Input
The propagated period time selection is based on circuit
with a low cost clock quartz of 32.768 kHz.
Pin 7, Test Logic, Figure 2, 3
To test the circuit in a reasonable time, it is possible to
control the divider (fo = 16 Hz) at Pin 7 as well as to feed
vin a higher frequency to the programmed residual counter
(fi 2 kHz).
Pin 8, Supply Voltage
An operating voltage of 4.5 V is necessary for the func-
tioning of the circuit, although an internal switch-on
monitoring allows it to operate with a voltage of 3.6 V.
This means that there is sufficient reliability for the per-
"formance of the circuit.
The circuit is designed for 12 V 10% with internal sup-
ply voltage limitation of typical 15 V. In case of higher
voltages there is a need of a series resistance and buffer
capacitance as shown in figure 1.
2 (7) TELEFUNKEN Semiconductors
Rev. A1, 30-May-96