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STMicroelectronics Electronic Components Datasheet

M24256-A Datasheet

256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines

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M24256-A pdf
M24256-A
256 Kbit Serial I C Bus EEPROM
With Two Chip Enable Lines
PRELIMINARY DATA
s Compatible with I2C Extended Addressing
s Two Wire I2C Serial Interface
Supports 400 kHz Protocol
s Single Supply Voltage:
– 4.5V to 5.5V for M24256-A
– 2.5V to 5.5V for M24256-AW
– 1.8V to 3.6V for M24256-AR
s 2 Chip Enable Inputs: up to four memories can
be connected to the same I2C bus
s Hardware Write Control
s BYTE and PAGE WRITE (up to 64 Bytes)
s RANDOM and SEQUENTIAL READ Modes
s Self-Timed Programming Cycle
s Automatic Address Incrementing
s Enhanced ESD/Latch-Up Behavior
s More than 100,000 Erase/Write Cycles
s More than 40 Year Data Retention
DESCRIPTION
These I2C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 32Kx8 bits, and operate down to 2.5 V
(for the M24256-AW), and down to 1.8 V (for the
M24256-AR).
The M24256-A is available in Plastic Dual-in-Line,
Plastic Small Outline and Thin Shrink Small Out-
line packages. The M24256-A is also available in
a chip-scale (SBGA) package.
Table 1. Signal Names
E0, E1
Chip Enable
SDA
Serial Data
SCL
Serial Clock
WC Write Control
VCC
VSS
Supply Voltage
Ground
8
1
PSDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
14
1
TSSOP14 (DL)
169 mil width
SBGA
SBGA7 (EA)
140 x 90 mil
8
1
SO8 (MW)
200 mil width
Figure 1. Logic Diagram
VCC
2
E0-E1
SCL
WC
M24256-A
SDA
VSS
AI02271C
April 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/20



STMicroelectronics Electronic Components Datasheet

M24256-A Datasheet

256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines

No Preview Available !

M24256-A pdf
M24256-A
Figure 2A. DIP Connections
Figure 2C. TSSOP Connections
M24256-A
E0 1
E1 2
8 VCC
7 WC
NC 3
6 SCL
VSS 4
5 SDA
AI02273C
Note: 1. NC = Not Connected
Figure 2B. SO Connections
E0
E1
NC
VSS
M24256-A
18
27
36
45
AI02272C
VCC
WC
SCL
SDA
Note: 1. NC = Not Connected
E0
E1
NC
NC
NC
NC
VSS
M24256-A
1 14
2 13
3 12
4 11
5 10
69
78
AI02388C
VCC
WC
NC
NC
NC
SCL
SDA
Note: 1. NC = Not Connected
Figure 2D. SBGA Connections (top view)
M24256-A
WC S1
VCC
S0
SDA
SCL VSS
AI03760
Table 2. Absolute Maximum Ratings 1
Symbol
Parameter
Value
Unit
TA
T STG
Ambient Operating Temperature
Storage Temperature
–40 to 125
–65 to 150
°C
°C
TLEAD
Lead Temperature during Soldering
PSDIP8: 10 sec
SO8: 40 sec
TSSOP14: t.b.c.
260
215
t.b.c.
°C
VIO Input or Output range
–0.6 to 6.5
V
VCC Supply Voltage
–0.3 to 6.5
V
VESD
Electrostatic Discharge Voltage (Human Body model) 2
Electrostatic Discharge Voltage (Machine model) 3
4000
200
V
V
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 )
3. EIAJ IC-121 (Condition C) (200 pF, 0 )
2/20



STMicroelectronics Electronic Components Datasheet

M24256-A Datasheet

256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines

No Preview Available !

M24256-A pdf
M24256-A
These memory devices are compatible with the
I2C extended memory standard. This is a two wire
serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4-
bit unique Device Type Identifier code (1010) in
accordance with the I2C bus definition.
The memory behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory in-
serts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af-
ter a NoAck for READ.
Power On Reset: VCC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re-
set (POR) circuit is included. The internal reset is
held active until the VCC voltage has reached the
POR threshold value, and all operations are dis-
abled – the device will not respond to any com-
mand. In the same way, when VCC drops from the
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any command. A stable and valid VCC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slow-
er clock, the master must have an open drain out-
put, and a pull-up resistor must be connected from
the SCL line to VCC. (Figure 3 indicates how the
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the master has
a push-pull (rather than open drain) output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to trans-
fer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to VCC. (Figure 3 indicates how the value of the
pull-up resistor can be calculated).
Chip Enable (E1, E0)
These chip enable inputs are used to set the value
that is to be looked for on the two least significant
bits (b2, b1) of the 7-bit device select code. These
inputs must be tied to VCC or VSS to establish the
device select code. When unconnected, the E1
and E0 inputs are internally read as VIL (see Table
7 and Table 8)
Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC=VIL) or disable (WC=VIH)
write instructions to the entire memory area. When
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC
20
16
12
8
4
0
10
fc = 100kHz
fc = 400kHz
100
CBUS (pF)
SDA
MASTER
SCL
RL
RL
CBUS
1000
CBUS
AI01665
3/20




Part Number M24256-A
Description 256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines
Maker STMicroelectronics
Total Page 20 Pages
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