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  ON Semiconductor Electronic Components Datasheet  

NCP51510 Datasheet

Termination Source / Sink Regulator

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NCP51510 pdf
NCP51510, NCV51510
3 Amp VTT Termination
Source / Sink Regulator for
DDR, DDR-2, DDR-3, DDR-4
The NCP51510 is a source/sink Double Data Rate (DDR)
termination regulator specifically designed for low input voltage and
low−noise systems where space is a key consideration. The
NCP51510 maintains a fast transient response and only requires a
minimum VTT load capacitance of 10 mF for output stability. The
NCP51510 supports remote sensing and all power requirements for
DDR VTT bus termination. The NCP51510 can also be used in
low−power chipsets and graphics processor cores that require
dynamically adjustable output voltages. The NCP51510 is available in
the thermally−efficient DFN10 Exposed Pad package, and is rated
both Green and Pb−Free.
Features
Generate DDR Memory Termination Voltage (VTT)
For DDR, DDR−2, DDR−3 and DDR−4 Source / Sink Currents
Supports Loads Up to ±3 A (Typ), Output is Over−Current Protected
Integrated MOSFETs with Thermal Shutdown Protection
Fast Load−Transient Response
PGOOD Output Pin to Monitor Status of VTT Output Regulation
SS Input Pin for Suspend Shutdown mode
VRI Input Reference for Flexible Voltage Tracking
VTTS Input for Remote Sensing (Kelvin Connection)
Built−in Soft−Start, Under Voltage Lockout
Small, Low−Profile 10−pin, 3 x 3 mm DFN Package
NCV51510MWTAG − Wettable Flank Option for Enhanced Optical
Inspection
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable*
This is a Pb−Free Device
Applications
DDR Memory Termination
Desktop PC’s, Notebooks, and Workstations
Servers and Networking equipment
Telecom/Datacom, GSM Base Station
Graphics Processor Core Supplies
Set Top Boxes, LCD−TV/PDP−TV, Copier/Printers
Supplies Power for Chipset/RAM as Low as 0.5 V
Active Source/Sink Bus Termination
www.onsemi.com
DFN10
CASE 485C
MARKING DIAGRAM
51510
ALYWG
G
51510 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
VRO 1
VCC 2
AGND 3
VRI 4
PGOOD 5
GND
(Top View)
10 PVCC
9 VTT
8 PGND
7 SS
6 VTTS
ORDERING INFORMATION
Device
Package Shipping
NCP51510MNTAG
NCV51510MNTAG*
NCV51510MWTAG*
DFN10
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 2
1
Publication Order Number:
NCP51510/D


  ON Semiconductor Electronic Components Datasheet  

NCP51510 Datasheet

Termination Source / Sink Regulator

No Preview Available !

NCP51510 pdf
NCP51510, NCV51510
PIN FUNCTION DESCRIPTION
Pin Number Pin Name
Pin Function
1 VRO OUTPUT − Buffered Output of VRI Reference Input pin.
2 VCC INPUT − Regulator Analog Power Input pin. Connect to the system supply voltage. Bypass VCC to AGND
with a 1 mF or greater ceramic capacitor.
3
AGND
Analog Ground
4 VRI INPUT − External Reference Input for VTT Output (see Figure 1 for typical application)
5
PGOOD
OUTPUT − VTT “Power Good” pin (open drain output)
6
VTTS
INPUT − Remote Sense Input for VTT. The VTTS pin provides accurate remote feedback sensing of the
VTT output.
7 SS INPUT − Suspend Shutdown Control Input. CMOS compatible. Logic HIGH = enable,
logic LOW = shutdown. Connect to VDDQ for normal operation.
8
PGND
Power Ground. Internally connected to Low−side MOSFET
9 VTT OUTPUT − Regulated Power Output pin
10
PVCC
INPUT − Regulator Power Input pin. Internally connected to High−side MOSFET
− THERMAL Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple vias
PAD
for maximum power dissipation performance.
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
PVCC to PGND
(Note 1)
−0.3 to 4.3
VCC to AGND
(Note 1)
VCC
−0.3 to 4.3
VRI, VRO, SS, PGOOD to AGND
VTT to PGND
(Note 1) − −0.3 to (VCC + 0.3)
V
(Note 1) − −0.3 to (PVCC + 0.3)
VTTS to AGND
(Note 1)
VTTS
−0.3 to (PVCC + 0.3)
PGND to AGND
PGND
−0.3 to +0.3
Storage Temperature
Operating Junction Temperature Range
Tstg −65 to 150
°C
TJ −40 to 125
ESD Capability, Human Body Model
(Note 2)
ESDHBM
2000
V
ESD Capability, Machine Model
(Note 2)
ESDMM
200
V
VTT Output Continuous RMS Current
100 sec
1 sec
±1.6
A
±2.5
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
DISSIPATION RATINGS
Package
10−Pin DFN
TA =705C Power Rate
1951 mW
Derating Factor Above TA = 705C
24.4 mW / °C
www.onsemi.com
2


Part Number NCP51510
Description Termination Source / Sink Regulator
Maker ON Semiconductor
Total Page 7 Pages
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