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  ON Semiconductor Electronic Components Datasheet  

NB3L8504S Datasheet

2.5V / 3.3V 1:4 Differential Input to LVDS Fanout Buffer / Translator

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NB3L8504S pdf
NB3L8504S
2.5 V / 3.3 V 1:4 Differential
Input to LVDS Fanout Buffer
/ Translator
Description
The NB3L8504S is a differential 1:4 LVDS fanout buffer/translator
with OE control for each differential output. The differential inputs
which can be driven by either a differential or single−ended input, can
accept various logic level standards such as LVPECL, LVDS, HSTL,
HCSL and SSTL. These signals are then translated to four identical
LVDS copies of the input up to 700 MHz. As such, the NB3L8504S is
ideal for Clock distribution applications that require low skew.
The NB3L8504S is offered in the TSSOP−16 package.
Features
Four Differential LVDS Outputs
Each Differential Output has OE Control
700 MHz Maximum Output Frequency
660 ps Max Output Rise and Fall Times, LVCMOS
Translates Differential Input to LVDS Levels
Additive Phase Jitter RMS: < 100 fs Typical
50 ps Maximum Output Skew
350 ps Maximum Part−to−part Skew
1.3 ns Maximum Propagation Delay
Operating Range: VCC = 2.5 V ± 5% or 3.3 V ± 10%
−40°C to +85°C Ambient Operating Temperature
16−Pin TSSOP, 4.4 mm x 5.0 mm x 0.925 mm
These are Pb−Free Devices
Applications
Telecom
Ethernet
Networking
SONET
www.onsemi.com
MARKING
DIAGRAM*
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
NB3L
8504
ALYWG
G
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
CLK
CLK
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 2
1
Publication Order Number:
NB3L8504S/D


  ON Semiconductor Electronic Components Datasheet  

NB3L8504S Datasheet

2.5V / 3.3V 1:4 Differential Input to LVDS Fanout Buffer / Translator

No Preview Available !

NB3L8504S pdf
NB3L8504S
Table 1. PIN DESCRIPTIONS AND CHARACTERISTICS
Pin Name
I/O
Description
1
OE0
LVTTL/LVCMOS Input Output Enable pin for Q0, Q0 outputs. Defaults High when left open; internal pull−up
resistor.
2
OE1
LVTTL/LVCMOS Input Output Enable pin for Q1, Q1 outputs. Defaults High when left open; internal pull−up
resistor.
3
OE2
LVTTL/LVCMOS Input Output Enable pin for Q2, Q2 outputs. Defaults High when left open; internal pull−up
resistor.
4 VDD
Power
3.3 V / 2.5 V Positive Supply Voltage.
5 GND
Power
3.3 V / 2.5 V Negative Supply Voltage.
6 CLK
Multi−Level Input
Non−inverting differential Clock input. Defaults Low when left open; internal pull−down
resistor.
7 CLK
Multi−Level Input
Inverting differential Clock input. Defaults to VDD/2 when left open; internal pull−up and
pull−down resistors.
8
OE3
LVTTL/LVCMOS Input Output Enable pin for Q3, Q3 outputs. Defaults High when left open; internal pull−up
resistor.
9 Q3
LVDS Output
Inverting differential Clock output.
10 Q3
LVDS Output
Non−inverting differential Clock output.
11 Q2
LVDS Output
Inverting differential Clock output.
12 Q2
LVDS Output
Non−inverting differential Clock output.
13 Q1
LVDS Output
Inverting differential Clock output.
14 Q1
LVDS Output
Non−inverting differential Clock output.
15 Q0
LVDS Output
Inverting differential Clock output.
16 Q0
LVDS Output
Non−inverting differential Clock output.
1. All VDD and GND pins must be externally connected to a power supply for proper operation.
OE0 1
OE1 2
OE2 3
VDD 4
GND 5
CLK 6
CLK 7
OE3 8
16 Q0
15 Q0
14 Q1
13 Q1
12 Q2
11 Q2
10 Q3
9 Q3
Figure 2. NB3L8504S Pinout, 16−pin TSSOP (Top View)
Table 2. OUTPUT ENABLE FUNCTION TABLE
OE[3:0]
Outputs – Q[0:3], Q[0:3]
LOW
High Impedance
HIGH (Default)
Active
www.onsemi.com
2


Part Number NB3L8504S
Description 2.5V / 3.3V 1:4 Differential Input to LVDS Fanout Buffer / Translator
Maker ON Semiconductor
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