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  ON Semiconductor Electronic Components Datasheet  

NB2309A Datasheet

3.3 V Zero Delay Clock Buffer

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NB2309A pdf
NB2309A
3.3 V Zero Delay
Clock Buffer
The NB2309A is a versatile, 3.3 V zero delay buffer designed to
distribute highspeed clocks. It accepts one reference input and drives
out nine lowskew clocks. It is available in a 16 pin package.
The 1H version of the NB2309A operates at up to 133 MHz, and
has higher drive than the 1 devices. All parts have onchip PLL’s that
lock to an input clock on the REF pin. The PLL feedback is onchip
and is obtained from the CLKOUT pad.
The NB2309A has two banks of four outputs each, which can be
controlled by the Select inputs as shown in the Select Input Decoding
Table. If all the output clocks are not required, Bank B can be
threestated. The select inputs also allow the input clock to be directly
applied to the outputs for chip and system testing purposes.
Multiple NB2309A devices can accept the same input clock and
distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycletocycle jitter. The input
and output propagation delay is guaranteed to be less than 350 ps, and
the output to output skew is guaranteed to be less than 250 ps.
The NB2309A is available in two different configurations, as shown
in the ordering information table. The NB2309A1 is the base part. The
NB2309Ax1H* is the high drive version of the 1 and its rise and fall
times are much faster than 1 part.
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Features
15 MHz to 133 MHz Operating Range, Compatible with CPU and
PCI Bus Frequencies
Zero Input Output Propagation Delay
Multiple LowSkew Outputs
OutputOutput Skew Less than 250 ps
DeviceDevice Skew Less than 700 ps
One Input Drives 9 Outputs, Grouped as 4 + 4 + 1
Less than 200 ps CycletoCycle Jitter is Compatible with PentiumR
Based Systems
Test Mode to Bypass PLL
Available in 16 Pin, 150 mil SOIC and 4.4 mm TSSOP
3.3 V Operation, Advanced 0.35 m CMOS Technology
These are PbFree Devices**
http://onsemi.com
MARKING
DIAGRAMS*
16
1
SOIC16
D SUFFIX
CASE 751B
16
1
TSSOP16
DT SUFFIX
CASE 948F
16
XXXXXXXXG
AWLYWW
1
16
XXXX
XXXX
ALYWG
G
1
XXXX = Device Code
A = Assembly Location
WL, L = Wafer Lot
Y = Year
W, WW = Work Week
G or G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
*x = C for Commercial; I for Industrial.
**For additional information on our PbFree strategy and soldering details,
please download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 4
1
Publication Order Number:
NB2309A/D


  ON Semiconductor Electronic Components Datasheet  

NB2309A Datasheet

3.3 V Zero Delay Clock Buffer

No Preview Available !

NB2309A pdf
NB2309A
REF
PLL
MUX
CLKOUT
CLKA1
CLKA2
CLKA3
S2
SELECT INPUT
DECODING
S1
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Figure 1. Block Diagram
Table 1. SELECT INPUT DECODING
CLKOUT
PLL
S2
S1
Clock A1 A4
Clock B1 B4
(Note 1)
Output Source
ShutDown
0
0
Threestate
Threestate
Driven
PLL
N
01
Driven
Threestate
Driven
PLL
N
10
Driven
Driven
Driven
Reference
Y
11
Driven
Driven
Driven
PLL
N
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the
reference and the output.
http://onsemi.com
2


Part Number NB2309A
Description 3.3 V Zero Delay Clock Buffer
Maker ON Semiconductor
Total Page 9 Pages
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