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VC16241ADGG Datasheet

16-bit buffer/line driver 3-State

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VC16241ADGG pdf
INTEGRATED CIRCUITS
74LVC16241A
16-bit buffer/line driver (3-State)
Product specification
Supersedes data of 1995 Dec 26
IC24 Data Handbook
1997 Jul 29
Philips
Semiconductors


NXP Semiconductors Electronic Components Datasheet

VC16241ADGG Datasheet

16-bit buffer/line driver 3-State

No Preview Available !

VC16241ADGG pdf
Philips Semiconductors
16-bit buffer/line driver (3-State)
Product specification
74LVC16241A
FEATURES
5 volt tolerant inputs/outputs for interfacing with 5V logic
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum
noise and ground bounce
Direct interface with TTL levels
DESCRIPTION
The 74LVC16241A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families. Inputs can be driven from either 3.3V or 5V
devices. In 3-State operation, outputs can handle 5V. These
features allow the use of these devices in a mixed 3.3V/5V
environment.
The 74LVC16241A is a 16-bit buffer/line driver with 3-State outputs.
The 3-State outputs are controlled by the output enable inputs nOE
and nOE. Schmitt-trigger action at all inputs makes the circuit highly
tolerant for slower input rise and fall times. The device can be used
as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer.
PIN CONFIGURATION
1OE 1
1Y0 2
1Y1 3
GND 4
1Y2 5
1Y3 6
VCC 7
2Y0 8
2Y1 9
GND 10
2Y2 11
2Y3 12
3Y0 13
3Y1 14
GND 15
3Y2 16
3Y3 17
VCC 18
4Y0 19
4Y1 20
GND 21
4Y2 22
4Y3 23
4OE 24
48 2OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 VCC
41 2A0
40 2A1
39 GND
38 2A2
37 2A3
36 3A0
35 3A1
34 GND
33 3A2
32 3A3
31 VCC
30 4A0
29 4A1
28 GND
27 4A2
26 4A3
25 3OE
SW00049
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 _C; tr = tf v 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
nAn to nYn
CL = 50pF
VCC = 3.3V
CI Input capacitance
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in mW):
PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL x VCC2 x fo) = sum of outputs.
TYPICAL
2.9
5.0
25
UNIT
ns
pF
pF
ORDERING INFORMATION
PACKAGES
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVC16241A DL
74LVC16241A DGG
NORTH AMERICA
VC16241A DL
VC16241A DGG
DWG NUMBER
SOT370-1
SOT362-1
1997 Jul 29
2 853-2006 18217


Part Number VC16241ADGG
Description 16-bit buffer/line driver 3-State
Maker NXP
Total Page 10 Pages
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