16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state 74LVCH162373A
• ESD protection:
exceeds 2000 V
exceeds 200 V
• 5 V tolerant input/output for
interfacing with 5 V logic
• Wide supply voltage range of
1.2 to 3.6 V
• Complies with JEDEC standard
• CMOS low power consumption
• MULTIBYTE™ flow-through
standard pin-out architecture
• Low inductance multiple power and
ground pins for minimum noise and
• Direct interface with TTL levels
• All data inputs have bus hold
• High impedance when VCC = 0
• Power off disables outputs,
permitting live insertion.
The 74LVC(H)162373A is a 16-bit D-type transparent latch featuring separate
D-type inputs for each latch and 3-state outputs for bus oriented applications.
One latch enable (LE) input and one output enable (OE) are provide for each
octal. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 V. These features allow the use of these devices in a
mixed 3.3 and 5 V environment.
The 74LVC(H)162373 consists of 2 sections of eight D-type transparent latches
with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the
latches. In this condition the latches are transparent, i.e. a latch output will
change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present at the
D-inputs a set-up time preceding the HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the eight latches are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of the OE input does not affect the state off latches.
The 74LVCH162373A bus hold data inputs eliminates the need for external pull
up resistors to hold unused inputs.
The 74LVC(H)162373A is designed with 30 Ω series termination resistors in
both HIGH and LOW output stages to reduce line noise.
FUNCTION TABLE (per section of eight bits)
See note 1.
Enable and read register
Latch and read register
Latch register and disable outputs
OE LE Dn
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
Q0 to Q7
1999 Aug 05