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Motorola Electronic Components Datasheet

MC88915FN70PLCC Datasheet

Low Skew CMOS PLL Clock Driver

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MC88915FN70PLCC pdf
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low Skew CMOS PLL Clock
Driver
MC88915
The MC88915 Clock Driver utilizes phase–locked loop
technology to lock its low skew outputs’ frequency and phase
onto an input reference clock. It is designed to provide clock
distribution for high performance PC’s and workstations.
The PLL allows the high current, low skew outputs to lock
onto a single clock input and distribute it with essentially zero
delay to multiple components on a board. The PLL also allows
the MC88915 to multiply a low frequency input clock and
distribute it locally at a higher (2X) system frequency. Multiple
88915’s can lock onto a single reference clock, which is ideal
for applications when a central system clock must be
distributed synchronously to multiple boards (see Figure 7).
Five “Q” outputs (QO–Q4) are provided with less than 500
ps skew between their rising edges. The Q5 output is inverted
(180° phase shift) from the “Q” outputs. The 2X_Q output runs
at twice the “Q” output frequency, while the Q/2 runs at 1/2 the
“Q” frequency.
The VCO is designed to run optimally between 20 MHz and
the 2X_Q Fmax specification. The wiring diagrams in Figure 5
detail the different feedback configurations which create
specific input/output frequency relationships. Possible
frequency ratios of the “Q” outputs to the SYNC input are 2:1,
1:1, and 1:2.
The FREQ_SEL pin provides one bit programmable
divide–by in the feedback path of the PLL. It selects between
divide–by–1 and divide–by–2 of the VCO before its signal
reaches the internal clock distribution section of the chip (see
the block diagram on page 2). In most applications
FREQ_SEL should be held high (÷1). If a low frequency
reference clock input is used, holding FREQ_SEL low (÷2) will
allow the VCO to run in its optimal range (>20 MHz).
In normal phase–locked operation the PLL_EN pin is held
high. Pulling the PLL_EN pin low disables the VCO and puts
the 88915 in a static “test mode”. In this mode there is no
frequency limitation on the input clock, which is necessary for
a low frequency board test environment. The second SYNC
input can be used as a test clock input to further simplify
board–level testing (see detailed description on page 11).
A lock indicator output (LOCK) will go high when the loop is
in steady–state phase and frequency lock. The LOCK output
will go low if phase–lock is lost or when the PLL_EN pin is low.
Under certain conditions the lock output may remain low, even
though the part is phase–locked. Therefore the LOCK output
signal should not be used to drive any active circuitry; it should
be used for passive monitoring or evaluation purposes only.
Yield Surface Modeling and YSM are trademarks of Motorola, Inc.
1/97
© Motorola, Inc. 1997
1
Features
Five Outputs (QO–Q4) with Output–Output Skew < 500
ps each being phase and frequency locked to the SYNC
input
The phase variation from part–to–part between the SYNC
and FEEDBACK inputs is less than 550 ps (derived from
the tPD specification, which defines the part–to–part
skew)
Input/Output phase–locked frequency ratios of 1:2, 1:1,
and 2:1 are available
Input frequency range from 5MHz – 2X_Q FMAX spec
Additional outputs available at 2X and +2 the system “Q”
frequency. Also a Q (180° phase shift) output available
All outputs have ±36 mA drive (equal high and low) at
CMOS levels, and can drive either CMOS or TTL inputs.
All inputs are TTL–level compatible
Test Mode pin (PLL_EN) provided for low frequency
testing. Two selectable CLOCK inputs for test or
redundancy purposes
RST VCC Q5 GND Q4 VCC 2X_Q
4 3 2 1 28 27 26
FEEDBACK 5
25
REF_SEL 6
24
SYNC[0] 7
23
Q/2
GND
Q3
VCC(AN)
RC1
8
9
22 VCC
21 Q2
GND(AN) 10
20 GND
SYNC[1] 11
19 LOCK
12 13 14 15 16 17 18
FREQ_SEL GND Q0 VCC Q1 GND PLL_EN
28–Lead Pinout (Top View)
FN SUFFIX
PLASTIC PLCC
CASE 776–02
ORDERING INFORMATION
MC88915FN55 PLCC
MC88915FN70 PLCC
REV 4


Motorola Electronic Components Datasheet

MC88915FN70PLCC Datasheet

Low Skew CMOS PLL Clock Driver

No Preview Available !

MC88915FN70PLCC pdf
MC88915
FEEDBACK
SYNC (0)
SYNC (1)
REF_SEL
0
M
U
X
1
PHASE/FREQ.
DETECTOR
LOCK
CHARGE PUMP/LOOP
FILTER
VOLTAGE
CONTROLLED
OSCILLATOR
EXTERNAL REC NETWORK
(RC1 Pin)
PLL_EN
01
MUX
DIVIDE
BY TWO
(÷1)
(÷2)
1
M
U
X
0
FREQ_SEL
RST
PIN SUMMARY
Pin Name Num I/O
Function
SYNC[0]
1 Input Reference clock input
SYNC[1]
1 Input Reference clock input
REF_SEL
1 Input Chooses reference between sync[0] & Sync[1]
FREQ_SEL 1 Input Selects Q output frequency
FEEDBACK 1 Input Feedback input to phase detector
RC1 1 Input Input for external RC network
Q(0–4)
5 Output Clock output (locked to sync)
Q5 1 Output Inverse of clock output
2x_Q 1 Output 2 x clock output (Q) frequency (synchronous)
Q/2 1 Output Clock output(Q) frequency ÷ 2 (synchronous)
LOCK
1 Output Indicates phase lock has been achieved (high when locked)
RST 1 Input Asynchronous reset (active low)
PLL_EN
1 Input Disables phase–lock for low freq. testing
VCC,GND
11
Power and ground pins (note pins 8, 10 are
“quiet” supply pins for internal logic only)
DQ
CP Q
R
DQ
CP
R
DQ
CP
R
DQ
CP
R
DQ
CP
R
DQ
CP
R
2x_Q
Q0
Q1
Q2
Q3
Q4
Q5
MOTOROLA
MC88915 Block Diagram
2
DQ
CP
R
Q/2
TIMING SOLUTIONS
BR1333 — Rev 6


Part Number MC88915FN70PLCC
Description Low Skew CMOS PLL Clock Driver
Maker Motorola
Total Page 13 Pages
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