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Motorola Electronic Components Datasheet

AN211A Datasheet

FIFELD EFFECT TRANSISTORS

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MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR APPLICATION NOTE
Order this document
by AN211A/D
NOTE: The theory in this application note is still applicable,
but some of the products referenced may be discontinued.
Field Effect Transistors in Theory
and Practice
AN211A
INTRODUCTION
There are two types of field-effect transistors, the Junction
Field-Effect Transistor (JFET) and the “Metal-Oxide
Semiconductor” Field-Effect Transistor (MOSFET), or
Insulated-Gate Field-Effect Transistor (IGFET). The
principles on which these devices operate (current controlled
by an electric field) are very similar — the primary difference
being in the methods by which the control element is made.
This difference, however, results in a considerable difference
in device characteristics and necessitates variances in circuit
design, which are discussed in this note.
DRAIN
DRAIN
GATE
GATE
SOURCE
SOURCE
NĆCHANNEL JFET
PĆCHANNEL JFET
JUNCTION FIELD-EFFECT TRANSISTOR (JFET)
In its simplest form the junction field-effect transistor starts
with nothing more than a bar of doped silicon that behaves
as a resistor (Figure 1a). By convention, the terminal into
which current is injected is called the source terminal, since,
as far as the FET is concerned, current originates from this
terminal. The other terminal is called the drain terminal.
Current flow between source and drain is related to the
drain-source voltage by the resistance of the intervening
material. In Figure 1b, p-type regions have been diffused into
the n-type substrate of Figure 1a leaving an n-type channel
between the source and drain. (A complementary p-type
device is made by reversing all of the material types.) These
p-type regions will be used to control the current flow
between the source and the drain and are thus called gate
regions.
As with any p-n junction, a depletion region surrounds
the p-n junctions when the junctions are reverse biased
(Figure 1c). As the reverse voltage is increased, the
depletion regions spread into the channel until they meet,
creating an almost infinite resistance between the source and
the drain.
If an external voltage is applied between source and drain
(Figure 1d) with zero gate voltage, drain current flow in the
channel sets up a reverse bias along the surface of the gate,
parallel to the channel. As the drain-source voltage
increases, the depletion regions again spread into the
channel because of the voltage drop in the channel which
reverse biases the junctions. As VDS is increased, the
depletion regions grow until they meet, whereby any further
increase in voltage is counterbalanced by an increase in the
depletion region toward the drain. There is an effective
increase in channel resistance that prevents any further
increase in drain current. The drain-source voltage that
causes this current limiting condition is called the “pinchoff”
voltage (Vp). A further increase in drain-source voltage
produces only a slight increase in drain current.
The variation in drain current (ID) with drain-source
voltage (VDS) at zero gate-source voltage (VGS) is shown
in Figure 2a. In the low-current region, the drain current is
linearly related to VDS. As ID increases, the “channel” begins
to deplete and the slope of the ID curve decreases. When
the VDS is equal to Vp, ID “saturates” and stays relatively
constant until drain-to-gate avalanche, VBR(DSS) is reached.
If a reverse voltage is applied to the gates, channel pinch-off
occurs at a lower ID level (Figure 2b) because the depletion
region spread caused by the reverse-biased gates adds to
that produced by VDS. Thus reducing the maximum current
for any value of VDS.
È ÈÈSOURCE
N
DRAIN
ÈÈ ÈÈÈÈ ÈÇÇÈ(a)
ÈÈÇÇÇÇÈÈGATE 1
SOURCE
GATE 1
P
N
P
DRAIN
ÈÈÈÇÇÇÇÇÇÈÈÈÇÇÇSOURCE
(-) DEPLETION ZONES
P
N
DRAIN
P
GATE 2
(b)
(-) GATE 2
(c)
ÈÈÈÇÇÇÈÈÈÇÇÇÇÇÇÈÈÈSOURCE
GATE 1
P
(+)
ID
P
DRAIN
ID
GATE 2
(d)
Figure 1. Development of Junction
Field-Effect Transistors
+VDS
VP LOCUS
ID VGS = 0
IP
ID VGS = 0
VGS = - 1 V
VGS = - 2 V
VP
VDS
V(BR)DSS
VDS
(a) (b)
Figure 2. Drain Current Characteristics
REV 0
©MMOoTtoOroRlaO, InLcA. 19S9E3MICONDUCTOR AFPPoLrICMAoTrIOeNInINfFoOrmRMaAtTioIOnNOn This Product,
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Motorola Electronic Components Datasheet

AN211A Datasheet

FIFELD EFFECT TRANSISTORS

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AN211A pdf
AN211A
Freescale Semiconductor, Inc.
Due to the difficulty of diffusing impurities into both sides
of a semiconductor wafer, a single ended geometry is
normally used instead of the two-sided structure discussed
above. Diffusion for this geometry (Figure 3) is from one side
only. The substrate is of p-type material onto which an n-type
channel is grown epitaxially. A p-type gate is then diffused
into the n-type epitaxial channel. Contact metallization
completes the structure.
The substrate, which functions as Gate 2 of Figure 1, is
of relatively low resistivity material to maximize gain. For the
same purpose, Gate 1 is of very low resistivity material,
allowing the depletion region to spread mostly into the n-type
channel. In most cases the gates are internally connected
together. A tetrode device can be realized by not making
this internal connection.
DRAIN
DRAIN
TYPE C
GATE
SOURCE
GATE
SUBSTRATE
SOURCE
SUBSTRATE
DRAIN
DRAIN
absence of gate voltage is extremely low because the
structure is analogous to two diodes connected back to back.
The metal area of the gate forms a capacitor with the
insulating layers and the semiconductor channel. The metal
area is the top plate; the substrate material and channel are
the bottom plate.
For the structure of Figure 4, consider a positive gate
potential (see Figure 5). Positive charges at the metal side
of the metal-oxide capacitor induce a corresponding negative
charge at the semiconductor side. As the positive charge
at the gate is increased, the negative charge “induced” in
the semiconductor increases until the region beneath the
oxide effectively becomes an n-type semiconductor region,
and current can flow between drain and source through the
“induced” channel. In other words, drain current flow is
“enhanced” by the gate potential. Thus drain current flow can
be modulated by the gate voltage; i.e. the channel resistance
is directly related to the gate voltage. The n-channel structure
may be changed to a p-channel device by reversing the
material types.
DRAIN
GATE
SOURCE
SOURCE
TYPE B
GATE
SOURCE
GATE
SUBSTRATE
SOURCE
SUBSTRATE
NĆCHANNEL MOSFET
PĆCHANNEL MOSFET
MOS FIELD-EFFECT TRANSISTORS (MOSFET)
The metal-oxide-semiconductor (MOSFET) operates with
a slightly different control mechanism than the JFET. Figure
4 shows the development. The substrate may be high
resistivity p-type material, as for the 2N4351. This time two
separate low-resistivity n-type regions (source and drain) are
diffused into the substrate as shown in Figure 4b. Next, the
surface of the structure is covered with an insulating oxide
layer and a nitride layer. The oxide layer serves as a
protective coating for the FET surface and to insulate the
channel from the gate. However the oxide is subject to
contamination by sodium ions which are found in varying
quantities in all environments. Such contamination results
in long term instability and changes in device characteristics.
Silicon nitride is impervious to sodium ions and thus is used
to shield the oxide layer from contamination. Holes are cut
into the oxide and nitride layers allowing metallic contact to
the source and drain. Then, the gate metal area is overlaid
on the insulation, covering the entire channel region and,
simultaneously, metal contacts to the drain and source are
made as shown in Figure 4d. The contact to the metal area
covering the channel is the gate terminal. Note that there
is no physical penetration of the metal through the oxide and
nitride into the substrate. Since the drain and source are
isolated by the substrate, any drain-to-source current in the
CHANNËËËËEL ËËËË(SËËËËUBPSËËËËTRPAITNDËËËËE) ËËËËPL ËËËËËËËËËËËËËËËËËËËËËËËËËËËË
CHANNEL LENGTH
Figure 3. Junction FET with Single-Ended Geometry
SOURCE
DRAIN
P
(SUBSTRATE)
NN
P
(SUBSTRATE)
(a) (b)
SILICON NITRATE
OXIDE
SiO2
Si3N4
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉN N
S G METAL D
NN
PP
(SUBSTRATE)
(SUBSTRATE)
(c) (d)
Figure 4. Development of Enhancement-Mode
N-Channel MOSFET
2 For More InformMaOtiToOnROOLnATShEiMsICPOrNoDdUuCcTtO, R APPLICATION INFORMATION
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Part Number AN211A
Description FIFELD EFFECT TRANSISTORS
Maker Motorola
Total Page 12 Pages
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