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Integrated Device Technology Electronic Components Datasheet

ICS83026I-01 Datasheet

1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER

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ICS83026I-01 pdf
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS83026I-01 is a low skew, 1-to-2 Dif-
ICS ferential-to-LVCMOS/LVTTL Fanout Buffer and
HiPerClockS™ a member of the HiPerClockS ™ family of
High Performance Clock Solutions from
IDT. The differential input can accept most dif-
ferential signal types (LVPECL, LVDS, LVHSTL, HCSL and
SSTL) and translate to two single-ended LVCMOS/LVTTL out-
puts. The small 8-lead SOIC footprint makes this device ideal
www.DataSheefto4Ur u.csoemin applications with limited board space.
FEATURES
Two LVCMOS / LVTTL outputs
Differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 350MHz
Output skew: 15ps (maximum)
Part-to-part skew: 600ps (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
Small 8 lead SOIC package saves board space
3.3V core, 3.3V, 2.5V or 1.8V output operating supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free RoHS
(6) packages
BLOCK DIAGRAM
CLK
nCLK
OE
Q0
Q1
83026BMI-01
PIN ASSIGNMENT
VDD
CLK
nCLK
OE
1
2
3
4
8 VDDO
7 Q0
6 Q1
5 GND
ICS83026I-01
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
VDD
CLK
nCLK
OE
1
2
3
4
8 VDDO
7 Q0
6 Q1
5 GND
ICS83026I-01
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
1 REV. A OCTOBER 22, 2007


Integrated Device Technology Electronic Components Datasheet

ICS83026I-01 Datasheet

1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER

No Preview Available !

ICS83026I-01 pdf
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1 VDD Power
Positive supply pin.
2
CLK
Input Pulldown Non-inverting differential clock input.
3
4
www.DataSheet4U.co5m
nCLK
OE
GND
Input
Input
Power
Pullup/
Pulldown
Pullup
Inverting differential clock input. VDD/2 default when left floating.
Output enable. When HIGH, outputs are enabled. When LOW, outputs are in
High Impedance State. LVCMOS / LVTTL interface levels.
Power supply ground.
6 Q1 Output
Clock output. LVCMOS / LVTTL interface levels.
7 Q0 Output
Clock output. LVCMOS / LVTTL interface levels.
8
VDDO
Power
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
CIN Input Capacitance
CPD
Power Dissipation Capacitance
(per output)
RPULLUP
RPULLDOWN
Input Pullup Resistor
Input Pulldown Resistor
ROUT
Output Impedance
Test Conditions
VDD, VDDO = 3.465V
VDD = 3.465V, VDDO = 2.625V
V = 3.465V, V = 1.95V
DD DDO
VDD, VDDO = 3.3V
VDD = 3.3V, VDDO = 2.5V
VDD = 3.3V, VDDO = 1.8V
Minimum
Typical
4
51
51
7
8
10
Maximum
17
16
15
Units
pF
pF
pF
pF
kΩ
kΩ
Ω
Ω
Ω
TABLE 3. CONTROL FUNCTION TABLE
Input
OE
0
1
Outputs
Q0, Q1
HiZ
Active
83026BMI-01
2 REV. A OCTOBER 22, 2007


Part Number ICS83026I-01
Description 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Maker Integrated Device Technology
Total Page 14 Pages
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