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Integrated Device Technology Electronic Components Datasheet

ICS83026I-01 Datasheet

1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER

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ICS83026I-01 pdf
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS83026I-01 is a low skew, 1-to-2 Dif-
ICS ferential-to-LVCMOS/LVTTL Fanout Buffer and
HiPerClockS™ a member of the HiPerClockS ™ family of
High Performance Clock Solutions from
IDT. The differential input can accept most dif-
ferential signal types (LVPECL, LVDS, LVHSTL, HCSL and
SSTL) and translate to two single-ended LVCMOS/LVTTL out-
puts. The small 8-lead SOIC footprint makes this device ideal
www.DataSheefto4Ur u.csoemin applications with limited board space.
FEATURES
Two LVCMOS / LVTTL outputs
Differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 350MHz
Output skew: 15ps (maximum)
Part-to-part skew: 600ps (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
Small 8 lead SOIC package saves board space
3.3V core, 3.3V, 2.5V or 1.8V output operating supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free RoHS
(6) packages
BLOCK DIAGRAM
CLK
nCLK
OE
Q0
Q1
83026BMI-01
PIN ASSIGNMENT
VDD
CLK
nCLK
OE
1
2
3
4
8 VDDO
7 Q0
6 Q1
5 GND
ICS83026I-01
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
VDD
CLK
nCLK
OE
1
2
3
4
8 VDDO
7 Q0
6 Q1
5 GND
ICS83026I-01
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
1 REV. A OCTOBER 22, 2007



Integrated Device Technology Electronic Components Datasheet

ICS83026I-01 Datasheet

1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER

No Preview Available !

ICS83026I-01 pdf
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1 VDD Power
Positive supply pin.
2
CLK
Input Pulldown Non-inverting differential clock input.
3
4
www.DataSheet4U.co5m
nCLK
OE
GND
Input
Input
Power
Pullup/
Pulldown
Pullup
Inverting differential clock input. VDD/2 default when left floating.
Output enable. When HIGH, outputs are enabled. When LOW, outputs are in
High Impedance State. LVCMOS / LVTTL interface levels.
Power supply ground.
6 Q1 Output
Clock output. LVCMOS / LVTTL interface levels.
7 Q0 Output
Clock output. LVCMOS / LVTTL interface levels.
8
VDDO
Power
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
CIN Input Capacitance
CPD
Power Dissipation Capacitance
(per output)
RPULLUP
RPULLDOWN
Input Pullup Resistor
Input Pulldown Resistor
ROUT
Output Impedance
Test Conditions
VDD, VDDO = 3.465V
VDD = 3.465V, VDDO = 2.625V
V = 3.465V, V = 1.95V
DD DDO
VDD, VDDO = 3.3V
VDD = 3.3V, VDDO = 2.5V
VDD = 3.3V, VDDO = 1.8V
Minimum
Typical
4
51
51
7
8
10
Maximum
17
16
15
Units
pF
pF
pF
pF
kΩ
kΩ
Ω
Ω
Ω
TABLE 3. CONTROL FUNCTION TABLE
Input
OE
0
1
Outputs
Q0, Q1
HiZ
Active
83026BMI-01
2 REV. A OCTOBER 22, 2007



Integrated Device Technology Electronic Components Datasheet

ICS83026I-01 Datasheet

1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER

No Preview Available !

ICS83026I-01 pdf
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
8 Lead SOIC
112.7°C/W (0 lfpm)
w w w . D a t 8a LSeahd TeSSeOtP4 U . c o m
101.7°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.71V TO 3.465V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
VDD Positive Supply Voltage
3.135 3.3 3.465
3.135 3.3 3.465
VDDO
Output Supply Voltage
2.375 2.5 2.625
1.71 1.8 1.89
IDD Power Supply Current
IDDO Output Supply Current
10
3
Units
V
V
V
V
mA
mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.375V TO 3.465V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH Input High Voltage OE
2
VIL Input Low Voltage OE
-0.3
IIH Input High Current OE
VDD = VIN = 3.465V
IIL Input Low Current OE
VDD = 3.465V, VIN = 0V
-150
VOH Output High Voltage; NOTE 1
VDDO = 3.135V
VDDO = 2.375V
2.6
1.8
VOL Output Low Voltage; NOTE 1
NOTE
1:
Outputs
terminated
with
50Ω
to
V /2.
DDO
See
Parameter
Measurement
Information
section,
"Output Load Test Circuit" diagrams.
VDD + 0.3
0.8
5
0.5
V
V
µA
µA
V
V
V
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
VIH Input High Voltage OE
VIL Input Low Voltage OE
IIH Input High Current OE
IIL Input Low Current OE
V Output High Voltage
OH
VOL Output Low Voltage
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
IOH = -100µA
IOH = -2mA
IOL = 100µA
IOL = 2mA
2
-0.3
-150
VDDO - 0.2
VDDO - 0.45
VDD + 0.3
0.8
5
0.2
0.45
Units
V
V
µA
µA
V
V
V
V
83026BMI-01
3 REV. A OCTOBER 22, 2007




Part Number ICS83026I-01
Description 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Maker Integrated Device Technology
Total Page 14 Pages
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