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Integrated Silicon Solution Electronic Components Datasheet

IS61QDP2B21M18A1 Datasheet

18Mb QUADP (Burst 2) Synchronous SRAM

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IS61QDP2B21M18A1 pdf
IS61QDP2B21M18A/A1/A2
IS61QDP2B251236A/A1/A2
1Mx18, 512Kx36
18Mb QUADP (Burst 2) Synchronous SRAM
(2.0 CYCLE READ LATENCY)
OCTOBER 2014
FEATURES
512Kx36 and 1Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data
valid window.
Separate independent read and write ports with
concurrent read and write operations.
Synchronous pipeline read with EARLY write
operation.
Double Data Rate (DDR) interface for read and
write input ports.
2.0 Cycle read latency.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control
registering at rising edges only.
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
Data valid pin (QVLD).
+1.8V core power supply and 1.5, 1.8V VDDQ, used
with 0.75, 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte
writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1
functions.
Byte Write capability.
Fine ball grid array (FBGA) package option:
13mmx15mm and 15mmx17mm body size
165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
ODT (On Die Termination) feature is supported
optionally on data input, K/K#, and BWx#.
The end of top mark (A/A1/A2) is to define options.
: Don’t care ODT function
and pin connection
1 : Option1
2 : Option2
Refer to more detail description at page 6 for each
ODT option.
DESCRIPTION
The and
are synchronous, high-
performance CMOS static random access memory (SRAM)
devices. These SRAMs have separate I/Os, eliminating the
need for high-speed bus turnaround. The rising edge of K
clock initiates the read/write operation, and all internal
operations are self-timed. Refer to the
for a description of the basic
operations of these
SRAMs. Read and
write addresses are registered on alternating rising edges of
the K clock. Read and write performed in double data rate.
The following are registered internally on the rising edge of
the K clock:
Read address
Read enable
Write enable
Data-in for early writes
The following are registered on the rising edge of the K#
clock:
Write address
Byte writes
Data-in for second burst addresses
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered half a cycle
earlier than the write address. The first data-in burst is
clocked at the same time as the write command signal, and
the second burst is timed to the following rising edge of the
K# clock.
During the burst read operation, the data-outs from the first
bursts are updated from output registers of the second rising
edge of the K# clock (starting two cycles later after read
command). The data-outs from the second bursts are
updated with the third rising edge of the K clock. The K and
K# clocks are used to time the data-outs.
The device is operated with a single +1.8V power supply and
is compatible with HSTL I/O interface.
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
Inc.t)epgotreantitael dliabSiliityliocf IontnegrSatoedluSitliicoonnS,oIluntiocn.,-Inwc iswawde.qiusasteil.ycporomtected under the circumstances
Rev. B
10/02/2014
1


Integrated Silicon Solution Electronic Components Datasheet

IS61QDP2B21M18A1 Datasheet

18Mb QUADP (Burst 2) Synchronous SRAM

No Preview Available !

IS61QDP2B21M18A1 pdf
IS61QDP2B21M18A/A1/A2
IS61QDP2B251236A/A1/A2
Package ballout and description
x36 FBGA Ball Configuration (Top View)
1 2 3 4 5 6 7 8 9 10
A CQ# NC/SA1 NC/SA1 W# BW2# K# BW1# R# NC/SA1 NC/SA1
B Q27 Q18 D18
SA BW3#
K
BW0#
SA
D17 Q17
C D27 Q28 D19 VSS SA SA SA VSS D16 Q7
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS VDDQ Q15
D6
F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
H Doff# VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD VDDQ Q12
D3
L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1
N D34 D26 Q25 VSS SA SA SA VSS Q10 D9
P Q35 D35 Q26 SA SA QVLD SA SA Q9 D0
R TDO TCK
SA
SA
SA ODT SA
SA
SA TMS
Notes:
The following balls are reserved for higher densities: 9A for 36M, 3A for 72M, 10A for 144Mb, and 2A for 288Mb.
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
x18 FBGA Ball Configuration (Top View)
12 3 456 7 8
A CQ# NC/SA1 NC/SA1 W# BW1# K# NC/SA1 R#
B NC
Q9
D9 SA NC
K
BW0#
SA
C NC NC D10 VSS SA SA SA VSS
D NC D11 Q10 VSS VSS VSS VSS VSS
9 10
SA NC/SA1
NC NC
NC Q7
NC NC
E NC
NC
Q11
VDDQ
VSS
VSS
VSS VDDQ NC
D6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
H Doff# VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
J NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
K NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS VDDQ NC
M NC NC D16 VSS VSS VSS VSS VSS NC
N NC D17 Q16 VSS SA SA SA VSS NC
P NC NC Q17 SA SA QVLD SA SA NC
NC
Q1
NC
D0
R TDO TCK
SA
SA
SA ODT SA
SA
SA TMS
Notes:
1. The following balls are reserved for higher densities: 3A for 36M, 10A for 72M, 2A for 144Mb, and 7A for 288Mb.
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/02/2014
2


Part Number IS61QDP2B21M18A1
Description 18Mb QUADP (Burst 2) Synchronous SRAM
Maker ISSI
Total Page 30 Pages
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