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Integrated Silicon Solution Electronic Components Datasheet

IS61QDB21M36 Datasheet

QUAD (Burst of 2) Synchronous SRAMs

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IS61QDB21M36 pdf
36 Mb (1M x 36. & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs
I
Features
• 1M x 36 or 2M x 18.
• On-chip delay-locked loop (DLL) for wide data
valid window.
• Separate read and write ports with concurrent
read and write operations.
• Synchronous pipeline read with early write oper-
ation.
• Double data rate (DDR) interface for read and
write input ports.
• Fixed 2-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K) for address and con-
trol registering at rising edges only.
• Two input clocks (C and C) for data output con-
trol.
JANUARY 2010
• Two echo clocks (CQ and CQ) that are delivered
simultaneously with data.
• +1.8V core power supply and 1.5, 1.8V VDDQ,
used with 0.75, 0.9V VREF.
• HSTL input and output levels.
• Registered addresses, write and read controls,
byte writes, data in, and data outputs.
• Full data coherency.
• Boundary scan using limited set of JTAG 1149.1
functions.
• Byte write capability.
• Fine ball grid array (FBGA) package
- 15mm x 17mm body size
- 1mm pitch
- 165-ball (11 x 15) array
• Programmable impedance output drivers via 5x
user-supplied precision resistor.
Description
The 36Mb IS61QDB21Mx36 and IS61QDB22Mx18
are synchronous, high-performance CMOS static
random access memory (SRAM) devices. These
These SRAMs have separate I/Os, eliminating the
need for high-speed bus turnaround. The rising
edge of K clock initiates the read/write operation,
and all internal operations are self-timed. Refer to
the Timing Reference Diagram for Truth Table
on page 8 for a description of the basic opera-
tions of these SRAMs.
The input address bus operates at double data rate.
The following are registered internally on the rising
edge of the K clock:
• Read address
• Read enable
• Write enable
• Byte writes
• Data-in for early writes
The following are registered on the rising edge of
the K clock:
• Write address
• Byte writes
• Data-in for second burst addresses
Byte writes can change with the corresponding data-
in to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be regis-
tered half a cycle earlier than the write address. The
first data-in burst is clocked at the same time as the
write command signal, and the second burst is timed
to the following rising edge of the K clock.
During the burst read operation, the data-outs from
the first burst are updated from output registers off
the second rising edge of the C clock (1.5 cycles
later). The data-outs from the second burst are
updated with the third rising edge of the C clock. The
K and K clocks are used to time the data-outs when-
ever the C and C clocks are tied high.
The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
1/6/2010
1


Integrated Silicon Solution Electronic Components Datasheet

IS61QDB21M36 Datasheet

QUAD (Burst of 2) Synchronous SRAMs

No Preview Available !

IS61QDB21M36 pdf
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs
I®
x36 FBGA Pinout (Top View)
1 2 3 4 5 6 7 8 9 10
A CQ VSS/SA NC/SA* W BW2 K BW1 R
SA VSS/SA
B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17
C D27 Q28 D19 VSS
SA
SA
SA VSS D16 Q7
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15
E Q29
D29
Q20
VDDQ
VSS
VSS
VSS VDDQ Q15
D6
F Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
G D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
J D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
K Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
L Q33
Q24
D24
VDDQ
VSS
VSS
VSS VDDQ D11
Q11
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1
N D34 D26 Q25 VSS
SA
SA
SA VSS Q10 D9
P Q35 D35 Q26
SA
SA
C
SA SA Q9 D0
R TDO
TCK
SA
SA
SA
C
SA SA SA TMS
Note: The following pins are reserved for higher densities: A3 for 64Mb, 10A for 144Mb, and 2A for 288Mb.
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
x18 FBGA Pinout (Top View)
123456789
A CQ VSS/SA* SA W BW1 K NC R SA
B NC Q9 D9 SA NC
K
BW0
SA
NC
C NC
NC
D10
VSS
SA
SA
SA VSS NC
D NC D11 Q10 VSS VSS VSS VSS VSS NC
E NC
NC
Q11
VDDQ
VSS
VSS
VSS VDDQ NC
F NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
G NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
K NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
L NC
Q15
D15
VDDQ
VSS
VSS
VSS VDDQ NC
M NC NC D16 VSS VSS VSS VSS VSS NC
N NC
D17 Q16 VSS
SA
SA
SA VSS NC
P NC
NC Q17 SA
SA
C
SA SA NC
R TDO
TCK
SA
SA
SA
C
SA SA
Note: The following pins are reserved for higher densities: 10A for 72Mb and 2A for 144Mb.
SA
10
VSS/SA*
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
2 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
1/6/2010


Part Number IS61QDB21M36
Description QUAD (Burst of 2) Synchronous SRAMs
Maker ISSI
Total Page 27 Pages
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