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Integrated Device Technology Electronic Components Datasheet

IDT29FCT520BT Datasheet

MULTILEVEL PIPELINE REGISTERS

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IDT29FCT520BT pdf
MULTILEVEL
PIPELINE REGISTERS
IDT29FCT520AT/BT/CT/DT
IDT29FCT521AT/BT/CT/DT
Integrated Device Technology, Inc.
FEATURES:
• A, B, C and D speed grades
• Low input and output leakage 1µA (max.)
• CMOS power levels
• True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• High drive outputs (-15mA IOH, 48mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
• Available in DIP, SOIC, SSOP, QSOP, CERPACK and
LCC packages
DESCRIPTION:
The IDT29FCT520AT/BT/CT/DT and IDT29FCT521AT/
BT/CT/DT each contain four 8-bit positive edge-triggered
registers. These may be operated as a dual 2-level or as a
single 4-level pipeline. A single 8-bit input is provided and any
of the four registers is available at the 8-bit, 3-state output.
These devices differ only in the way data is loaded into and
between the registers in 2-level operation. The difference is
illustrated in Figure 1. In the IDT29FCT520AT/BT/CT/DT
when data is entered into the first level (I = 2 or I = 1), the
existing data in the first level is moved to the second level. In
the IDT29FCT521AT/BT/CT/DT, these instructions simply
cause the data in the first level to be overwritten. Transfer of
data to the second level is achieved using the 4-level shift
instruction (I = 0). This transfer also causes the first level to
change. In either part I=3 is for hold.
FUNCTIONAL BLOCK DIAGRAM
D0 -D7
8
I0,I1 2
REGISTER
CONTROL
CLK 1
OCTAL REG. A1
OCTAL REG. A2
MUX
OCTAL REG. B1
OCTAL REG. B2
S0 ,S1 2
MUX
OE
8
Y0 -Y7
2619 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1994 Integrated Device Technology, Inc.
6.2
APRIL 1994
DSC-4215/4
1


Integrated Device Technology Electronic Components Datasheet

IDT29FCT520BT Datasheet

MULTILEVEL PIPELINE REGISTERS

No Preview Available !

IDT29FCT520BT pdf
IDT29FCT520AT/BT/CT/DT, 521AT/BT/CT/DT
MULTILEVEL PIPELINE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
I0
I1
D0
D1
D2
D3
D4
D5
D6
D7
CLK
GND
1 24
2 23
3 22
4 P24-1 21
5 D24-1 20
SO24-2
6 SO24-7 19
7 SO24-8* 18
8 & 17
9 E24-1 16
10 15
11 14
12 13
Vcc
S0
S1
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
OE
2619 drw 02
DIP/SOIC/SSOP/QSOP/CERPACK
*FCT520 only
TOP VIEW
INDEX
4 3 2 28 27 26
D1 5
D2 6
1 25 Y0
24 Y1
D3 7
23 Y2
NC 8
L28-1
22 NC
D4 9
21 Y3
D5 10
20 Y4
D6 11
19 Y5
12 13 14 15 16 17 18
2619 drw 03
LCC
TOP VIEW
DEFINITION OF FUNCTIONAL TERMS
Pin Names
Description
Dn Register input Port.
CLK
Clock input. Enter data into registers on LOW-
to-HIGH transitions.
I0, I1
Instruction inputs. See Figure 1 and
struction Control Tables.
in-
S0, S1
OE
Multiplexer select. Inputs either register A1, A2,
B1 or B2 data to be available at the output port.
Output enable for 3-state output port.
Yn Register output port.
REGISTER SELECTION
S1 S0
00
01
10
11
Register
B2
B1
A2
A1
2619 tbl 02
2619 tbl 01
DUAL 2-LEVEL
SINGLE 4-LEVEL
IDT29FCT520T
A1 B1
A2 B2
I=2
A1 B1
A2 B2
I=1
A1 B1
A2 B2
I=0
IDT29FCT521T
NOTE:
1. I = 3 for hold.
A1 B1
A2 B2
I=2
A1 B1
A2 B2
I=1
Figure 1. Data Loading in 2-Level Operation
6.2
A1 B1
A2 B2
I=0
2619 drw 04
2


Part Number IDT29FCT520BT
Description MULTILEVEL PIPELINE REGISTERS
Maker IDT
Total Page 7 Pages
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