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Integrated Device Technology Electronic Components Datasheet

IDT2305 Datasheet

3.3V ZERO DELAY CLOCK BUFFER

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IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY
CLOCK BUFFER
IDT2305
FEATURES:
• Phase-Lock Loop Clock Distribution
• 10MHz to 133MHz operating frequency
• Distributes one clock input to one bank of five outputs
• Zero Input-Output Delay
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• IDT2305-1 for Standard Drive
• IDT2305-1H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Power down mode
• Available in SOIC package
DESCRIPTION:
The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one
reference input, and drives out five low skew clocks. The -1H version of this
device operates, up to 133MHz frequency and has a higher drive than the
-1 device. All parts have on-chip PLLs which lock to an input clock on the
REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT
pad. In the absence of an input clock, the IDT2305 enters power down. In
this mode, the device will draw less than 25µA, the outputs are tri-stated,
and the PLL is not running, resulting in a significant reduction of power.
The IDT2305 is characterized for both Industrial and Commercial
operation.
FUNCTIONAL BLOCK DIAGRAM
1
REF
PLL
Control
Logic
8
CLKOUT
3
CLK1
2 CLK2
5 CLK3
7
CLK4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL
c 2001 Integrated Device Technology, Inc.
TEMPERATURE
1
RANGES
APRIL 2001
DSC 5174/4


Integrated Device Technology Electronic Components Datasheet

IDT2305 Datasheet

3.3V ZERO DELAY CLOCK BUFFER

No Preview Available !

IDT2305 pdf
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
PIN CONFIGURATION
REF
CLK2
CLK1
GND
1
2
3
4
8
7
6
5
SOIC
TOP VIEW
APPLICATIONS:
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
CLKOUT
CLK4
VDD
CLK3
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Max. Unit
VDD
Supply Voltage Range
–0.5 to +4.6 V
VI (2)
Input Voltage Range (REF)
–0.5 to +5.5 V
VI
Input Voltage Range
–0.5 to
V
(except REF)
VDD+0.5
IIK (VI < 0)
Input Clamp Current
–50 mA
IO (VO = 0 to VDD) ContinuousOutputCurrent
±50 mA
VDD or GND
Continuous Current
±100 mA
TA = 55°C
Maximum Power Dissipation
0.7
W
(in still air)(3)
TSTG
Operating
StorageTemperatureRange
Commercial Temperature
–65 to +150
0 to +70
°C
°C
Temperature
Range
Operating
Temperature
IndustrialTemperature
Range
-40 to +85 °C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
PIN DESCRIPTION
Pin Name
REF(1)
CLK2(2)
CLK1(2)
GND
CLK3(2)
VDD
CLK4(2)
CLKOUT(2)
Pin Number
1
2
3
4
5
6
7
8
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
Type
IN
Out
Out
Ground
Out
PWR
Out
Out
Functional Description
Input reference clock, 5 Volt tolerant input
Output clock
Output clock
Ground
Output clock
3.3V Supply
Output clock
Output clock, internal feedback on this pin
2


Part Number IDT2305
Description 3.3V ZERO DELAY CLOCK BUFFER
Maker IDT
Total Page 10 Pages
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