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Integrated Device Technology Electronic Components Datasheet

ICS9UMS9610 Datasheet

PC MAIN CLOCK

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ICS9UMS9610 pdf
PC MAIN CLOCK
Recommended Application:
Poulsbo Based Ultra-Mobile PC (UMPC) - CK610
Output Features:
• 3 - CPU low power differential push-pull pairss
• 3 - SRC low power differential push-pull pairs
• 1 - LCD100 SSCD low power differential
push-pull pair
• 1 - DOT96 low power differential push-pull
pair
• 1 - REF, 14.31818MHz, 3.3V SE output
Pin Configuration
Advance Information
ICS9UMS9610
Features/Benefits:
• Supports Dothan ULV CPUs with 100 to
200 MHz CPU outputs
• Dedicated TEST/SEL and TEST/MODE pins
saves isolation resistors on pins
• CPU STOP# input for power manangment
• Fully integrated Vreg
• Integrated series resistors on differential
outputs
• 1.5V VDD IO, 1.5V VDD core, 3.3V VDD
supply pin for REF
48 47 46 45 44 43 42 41 40 39 38 37
CPU_STOP#_3.3 1
36 *CR#2_1.5
CLKPWRGD#/PD_3.3 2
35 SRCT2_LPR
X2 3
34 SRCC2_LPR
X1 4
33 GNDSRC
VDDREF_3.3 5
32 SRCT1_LPR
REF_3.3_2x 6
GNDREF 7
9UMS9610
31 SRCC1_LPR
30 VDDIO_1.5
VDDCORE_1.5 8
29 VDDCORE_1.5
FSC_L_1.5 9
28 *CR#1_1.5
TEST_MODE_1.5 10
27 SRCT0_LPR
TEST_SEL_1.5 11
26 SRCC0_LPR
SCLK_3.3 12
25 GNDSRC
13 14 15 16 17 18 19 20 21 22 23 24
IDTTM/ICSTM PC MAIN CLOCK
48-pin MLF, 6x6 mm, 0.4mm pitch
* indicates inputs with internal pull up of ~10Kohm to 1.5V
1
1336—07/21/08


Integrated Device Technology Electronic Components Datasheet

ICS9UMS9610 Datasheet

PC MAIN CLOCK

No Preview Available !

ICS9UMS9610 pdf
ICS9UMS9610
PC MAIN CLOCK
Advance Information
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1 CPU_STOP#_3.3
IN This active-low input stops all CPU clocks that are set to be stoppable.
This level sensitive strobe determines when latch inputs are valid and are
2 CLKPWRGD#/PD_3.3 IN ready to be sampled. When high, this asynchronous input places the
device into the power down state.
3 X2
OUT Crystal output, Nominally 14.318MHz
4 X1
IN Crystal input, Nominally 14.318MHz.
5 VDDREF_3.3
PWR Power pin for the XTAL and REF clocks, nominal 3.3V
6 REF_3.3_2x
OUT 3.3V 14.318 MHz reference clock. Default 2 load drive strength
7 GNDREF
GND Ground pin for the REF outputs.
8 VDDCORE_1.5
PWR 1.5V power for the PLL core
9 FSC_L_1.5
IN Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. 1.5V Max input voltage.
TEST_MODE is a real time input to select between Hi-Z and REF/N divider
10 TEST_MODE_1.5
IN mode while in test mode. Refer to Test Clarification Table. Max input
voltage is 1.5V.
Logic Level
(V)
3.3
3.3
N/A
1.5
3.3
3.3
0
1.5
1.5
1.5
11 TEST_SEL_1.5
TEST_SEL: latched input to select TEST MODE. Max input voltage is 1.5V
IN 1 = All outputs are tri-stated for test
0 = All outputs behave normally.
1.5
12 SCLK_3.3
13 SDATA_3.3
14 VDDCORE_1.5
15 VDDIO_1.5
16 DOT96C_LPR
17 DOT96T_LPR
18 GNDDOT
19 GNDLCD
20 LCD100C_LPR
21 LCD100T_LPR
22 VDDIO_1.5
23 VDDCORE_1.5
24 *CR#0_1.5
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 1.5V power for the PLL core
PWR Power supply for low power differential outputs, nominal 1.5V.
Complement clock of low power differential pair for 96.00MHz DOT clock.
OUT No 50ohm resistor to GND needed. No Rs needed.
OUT
True clock of low power differential pair for 96.00MHz DOT clock. No
50ohm resistor to GND needed. No Rs needed.
GND Ground pin for DOT clock output
GND Ground pin for LCD clock output
Complement clock of low power differential pair for LCD100 SS clock. No
OUT 50ohm resistor to GND needed. No Rs needed.
OUT
True clock of low power differential pair for LCD100 SS clock. No 50ohm
resistor to GND needed. No Rs needed.
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR 1.5V power for the PLL core
IN 1.5V Clock request for SRC0, 0 = enable, 1 = disable
3.3
3.3
1.5
1.5
0.8
0.8
0
0
0.8
0.8
1.5
1.5
1.5
Input Level
Tolerance (V)
3.3
3.3
N/A
1.5
3.3
N/A
N/A
1.5
1.5
3.3
3.3
3.3
3.3
1.5
1.5
N/A
N/A
N/A
N/A
N/A
N/A
1.5
1.5
1.5
IDTTM/ICSTM PC MAIN CLOCK
2
1336—07/21/08


Part Number ICS9UMS9610
Description PC MAIN CLOCK
Maker IDT
Total Page 20 Pages
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