http://www.www.datasheet4u.com

900,000+ Datasheet PDF Search and Download

Datasheet4U offers most rated semiconductors datasheets pdf




Integrated Device Technology Electronic Components Datasheet

ICS8S89874I Datasheet

1:2 Differential-to-LVPECL Buffer/Divider

No Preview Available !

ICS8S89874I pdf
1:2 Differential-to-LVPECL Buffer/Divider
ICS8S89874I
DATA SHEET
General Description
The ICS8S89874I is a high speed 1:2 Differential-to- LVPECL Buffer/
Divider. The ICS8S89874I has a selectable ÷1, ÷2, ÷4, ÷8, ÷16
output divider, which allows the device to be used as either a 1:2
fanout buffer or frequency divider. The clock input has internal
termination resistors, allowing it to interface with several differential
signal types while minimizing the number of required external
components. The device is packaged in a small, 3mm x 3mm
VFQFN package, making it ideal for use on space-constrained
boards.
Features
Two LVPECL/ECL output pairs
Frequency divide select options: ÷1 (pass through), ÷2, ÷4, ÷8,
÷16
IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
Output frequency: 2GHz (maximum)
Output skew: 15ps (maximum)
Part-to-part skew: 250ps (maximum)
Additive phase jitter, RMS: 0.20ps (typical)
LVPECL supply voltage range: 2.375V to 3.63V
ECL supply voltage range: -3.63V to -2.375V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
S2 Pullup
nRESET Pullup
Enable
FF
Enable
MUX
IN
50
VT
50
nIN
S0 Pullup
S1 Pullup
Decoder
VREF_AC
00 ÷2
01 ÷4
10 ÷8
11 ÷16
0
1
Pin Assignment
16 15 14 13
Q0 1
12 IN
nQ0 2
11 VT
Q1 3
10 VREF_AC
Q0
nQ1 4
9 nIN
56 78
nQ0
Q1
nQ1 ICS8S89874I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
ICS8S89874BKI REVISION A OCTOBER 22, 2010
1
©2010 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

ICS8S89874I Datasheet

1:2 Differential-to-LVPECL Buffer/Divider

No Preview Available !

ICS8S89874I pdf
ICS8S89874I Data Sheet
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
Q0, nQ0
Output
3, 4
Q1, nQ1
Output
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
5, 15, 16 S2, S1, S0
Input
Pullup Select pins. LVCMOS/LVTTL interface levels.
6 nc Unused
No connect.
7, 14
8
9
10
11
12
13
Vcc
nRESET
nIN
VREF_AC
VT
IN
VEE
Power
Input
Input
Output
Input
Input
Power
Pullup
Positive supply pins.
When LOW, resets the divider. Pulled HIGH when left unconnected. Input threshold
is VCC/2. Includes a 37kpullup resistor. LVTTL/LVCMOS interface levels.
Inverting differential LVPECL clock input. RT = 50termination to VT.
Reference voltage for AC-coupled applications.
Termination input.
Non-inverting LVPECL differential clock input. RT = 50termination to VT.
Negative supply pin.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
RPULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
k
ICS8S89874BKI REVISION A OCTOBER 22, 2010
2
©2010 Integrated Device Technology, Inc.


Part Number ICS8S89874I
Description 1:2 Differential-to-LVPECL Buffer/Divider
Maker IDT
Total Page 19 Pages
PDF Download
ICS8S89874I pdf
Download PDF File
ICS8S89874I pdf
View for Mobile






Related Datasheet

1 ICS8S89874I 1:2 Differential-to-LVPECL Buffer/Divider IDT
IDT
ICS8S89874I pdf




Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

site map

webmaste! click here

contact us

Buy Components