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Integrated Device Technology Electronic Components Datasheet

ICS843S2807 Datasheet

CRYSTAL-TOLVPECL/LVDS/LVCMOS CLOCK GENERATOR

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ICS843S2807 pdf
PRELIMINARY
FEMTOCLOCK™ CRYSTAL-TO-
LVPECL/LVDS/LVCMOS CLOCK GENERATOR
ICS843S2807
GENERAL DESCRIPTION
ICS843S2807 is a low phase noise Clock Generator
ICS and is a member of the HiperClockS™ family of high
HiPerClockS™ performance clock solutions from IDT. The device
provides five banks of outputs and a reference clock.
The banks can be enabled by using a common output
enable pin. A 25MHz crystal is used to generate the 50MHz,
66.67MHz, 87.5MHz, 100MHz, 125MHz, 133MHz and 350MHz
frequencies.
FEATURES
Five banks of outputs:
Bank A: one single-ended (QA0) LVCMOS output at: 133MHz
and one (QA1/nQA1) LVPECL output at: 66.67MHz, 100MHz
and 125MHz
Bank B: two (QB0, QB1) LVCMOS outputs at: 50MHz
Bank C: one (QC0/nQC0) differential LVPECL output at: 87.5MHz
Bank D: one (QD0/nQD0) differential LVDS output at: 350MHz
One single-ended LVCMOS reference clock output at: 25MHz
PIN ASSIGNMENT
Crystal input frequency: 25MHz
Maximum output frequency: 350MHz
±5% frequency margining
Full 3.3V operating supply
F_SEL0
F_SEL1
VCC
XTAL_IN
XTAL_OUT
VEE
VCCA2
RESET
32 31 30 29 28 27 26 25
1 24
2 23
3 ICS843S2807 22
4
32-Lead LQFP
7mm x 7mm x 1.4mm
21
5 package body 20
6 Y Package 19
7 Top View 18
8 17
VCC
QA1
nQA1
VCCA1
VEE
QC0
nQC0
VCC
9 10 11 12 13 14 15 16
F_SEL[1:0] Pullup
PLL_BYPASS Pulldown
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS6)
packages
BLOCK DIAGRAM
2
÷5.2631
LVCMOS - 25MHz
REF_OUT
LVCMOS - 133MHz
QA0
XTAL_IN
XTAL_OUT
25MHz
OSC
Phase
Detector
VCO
700MHz
1
÷5.6,
0 ÷7,
÷10.5
LVPECL - 66.67/100/
125MHz
QA1
nQA1
LVCMOS - 50MHz
QB0
÷28 ÷14
±5%
Frequency
Margining
QB1
LVPECL - 87.5MHz
QC0
÷8
nQC0
MARGIN Pulldown
LVDS - 350MHz
QD0
÷2
nQD0
MARGIN_MODE Pulldown
RESET Pulldown
OE Pullup
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT/ ICSLVPECL/LVDS/LVCMOS CLOCK GENERATOR
1
ICS843S2807BY REV. A JANUARY 30, 2008


Integrated Device Technology Electronic Components Datasheet

ICS843S2807 Datasheet

CRYSTAL-TOLVPECL/LVDS/LVCMOS CLOCK GENERATOR

No Preview Available !

ICS843S2807 pdf
ICS843S2807
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
1,
2
3, 16, 17, 24
4,
5
6, 13,
20, 27, 32
7, 21
8
Name
F_SEL0,
F_SEL1
VCC
XTAL_IN,
XTAL_OUT
V
EE
V VCCA2, CCA1
RESET
Type
Input Pullup
Power
Input
Power
Description
Frequency select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
Core supply pins.
Crystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Negative supply pins.
Power
Analog supply pins.
Input Pulldown Resets the dividers and PLL. LVCMOS/LVTTL interface levels.
9
10
11
12
14, 15
OE
MARGIN
MARGIN_MODE
PLL_BYPASS
QD0, nQD0
Input
Input
Input
Input
Output
Pullup
Pulldown
Pulldown
Pulldown
Output enable pin. LVCMOS/LVTTL interface levels.
Selects between the margin and normal mode.
LVCMOS/LVTTL interface levels. See Table 3B.
Selects between ±5% margin.
LVCMOS/LVTTL interface levels. See Table 3B.
Selects between the PLL and XTAL as the input to the dividers.
When LOW, selects PLL. When HIGH, selects XTAL.
LVCMOS/LVTTL interface levels.
Differential Bank D clock outputs. LVDS interface levels.
18, 19
nQC0, QC0 Output
Differential Bank C clock outputs. LVPECL interface levels.
22, 23
nQA1, QA1 Output
Differential Bank A clock outputs. LVPECL interface levels.
25, 30
26
VCCO_LVCMOS
QA0
Power
Output
Output supply pins for LVCMOS/LVTTL outputs.
Single-ended Bank A clock output.
LVCMOS/LVTTL interface levels. 15Ω impedance.
28, 29
QB1, QB0
Output
Single-ended Bank B clock outputs.
LVCMOS/LVTTL interface levels. 15Ω impedance.
31
REF_OUT
Output
Reference clock output. LVCMOS/LVTTL interface levels.
15Ω impedance.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
C
PD
RPULLDOWN
RPULLUP
ROUT
Parameter
Input Capacitance
Power
Dissipation Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Output Impedance
QA0,
QB0, QB1,
REF_OUT
QA0,
QB0, QB1,
REF_OUT
Test Conditions
Minimum Typical Maximum Units
4 pF
VCC, VCCO_LVCMOS = 3.465V
TBD
51
51
pF
kΩ
kΩ
VCCO_LVCMOS = 3.465V
15 Ω
IDT/ ICSLVPECL/LVDS/LVCMOS CLOCK GENERATOR
2
ICS843S2807BY REV. A JANUARY 30, 2008


Part Number ICS843S2807
Description CRYSTAL-TOLVPECL/LVDS/LVCMOS CLOCK GENERATOR
Maker IDT
Total Page 14 Pages
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