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ICS552-03 Datasheet Preview

ICS552-03 Datasheet

LOW SKEW 1 TO 8 CLOCK BUFFER

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ICS552-03
LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X)
Description
The ICS552-03 is a low skew, single input to eight
output clock buffer. Four of the outputs are exact copies
of the input, while the other four are divide by 2 copies
of the input. It is part of ICS’ Clock BlocksTM family. See
the ICS553 for a 1 to 4 low skew buffer, or the
ICS552-02 for a 1 to 8 low skew buffer without divide by
2. For more than 8 outputs see the MK74CBxxx
BuffaloTM series of clock drivers.
ICS makes many non-PLL and PLL based low skew
output devices as well as Zero Delay Buffers to
synchronize clocks. Contact us for all of your clocking
needs.
Features
Low skew outputs (50 ps maximum)
Packaged in 16 pin TSSOP
Low power CMOS technology
Operating Voltages of 2.5 V to 5 V
Output Enable pin tri-states outputs
Low skew between 1X and 1/2X outputs (100 ps
maximum)
One bank of 4 outputs at 1X
One bank of 4 outputs at 1/2X
5V tolerant input clocks
Input clock multiplexer
Block Diagram
INA 1
INB 0
D iv id e
by 2
Q0
Q1
Q2
Q3
P0
P1
P2
P3
SELA
OE
MDS 552-03 B
1
Revision 052501
Integrated Circuit Systems q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com



ICST
ICST

ICS552-03 Datasheet Preview

ICS552-03 Datasheet

LOW SKEW 1 TO 8 CLOCK BUFFER

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ICS552-03 pdf
ICS552-03
LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X)
Pin Assignment
OE
VDD
Q0
Q1
Q2
Q3
GND
INB
1
2
3
4
5
6
7
8
16 SELA
15 VDD
14 P3
13 P2
12 P1
11 P0
10 GND
9 INA
16 Pin 173 Mil (0.65mm) TSSOP
Input Source Select
SELA
0
1
Input
INB
INA
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
OE
VDD
Q0
Q1
Q2
Q3
GND
INB
INA
GND
P0
P1
P2
P3
VDD
SELA
Pin
Type
Input
Power
Output
Output
Output
Output
Power
Input
Input
Power
Output
Output
Output
Output
Power
Input
Pin Description
Output Enable. Tri-states outputs when low.Internal Pull-up resistor
Connect to +2.5 V, +3.3 V or +5.0 V. Must be the same as pin 15
Clock Output Q0
Clock Output Q1
Clock Output Q2
Clock Output Q3
Ground
Clock Input B. 5 V tolerant input
Clock Input A. 5 V tolerant input
Ground
Clock Output P0
Clock Output P1
Clock Output P2
Clock Output P3
Connect to +2.5 V, +3.3 V or +5.0 V. Must be the same as pin 2
Selects either INA or INB. Internal pull-up resistor
External Components
A minimum number of external components are required for proper operation. Decoupling capacitors of
0.01 µF should be connected between VDD on pin 2 and GND on pin 7,and between VDD on pin 15 and
GND on pin 10, as close to the device as possible. A 33 series terminating resistor should be used on
each clock output if the trace is longer than 1 inch.
To achieve the low output skews that the ICS552-03 is capable of, careful attention must be paid to board
layout. Essentially, all 8 outputs must have identical terminations, identical loads, and identical trace
geometries. If they do not, the output skew will be degraded. For example, using a 30 series termination
on one output (with 33on the others) will cause at least 15 ps of skew.
MDS 552-03 B
2
Revision 052501
Integrated Circuit Systems q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com


Part Number ICS552-03
Description LOW SKEW 1 TO 8 CLOCK BUFFER
Maker ICST
Total Page 6 Pages
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