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Cypress Semiconductor Electronic Components Datasheet

CYK256K16MCCB Datasheet

4-Mbit (256K x 16) Pseudo Static RAM

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CYK256K16MCCB pdf
CYK256K16MCCB
MoBL3™
4-Mbit (256K x 16) Pseudo Static RAM
Features
• Wide voltage range: 2.70V–3.30V
• Access time: 55 ns, 60 ns and 70 ns
• Ultra-low active power
— Typical active current: 1 mA @ f = 1 MHz
— Typical active current: 8 mA @ f = fmax (70-ns speed)
• Ultra low standby power
www.DataASuhteoemt4aUti.ccopmower-down when deselected
• CMOS for optimum speed/power
• Offered in a 48-ball BGA package
Functional Description[1]
The CYK256K16MCCB is a high-performance CMOS Pseudo
static RAM organized as 256K words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life(MoBL®) in
portable applications such as cellular telephones. The device
can be put into standby mode when deselected (CE HIGH or
both BHE and BLE are HIGH). The input/output pins (I/O0
through I/O15) are placed in a high-impedance state when:
deselected (CE HIGH), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE LOW) and Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through
I/O7) is written into the location specified on the address pins
(A0 through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip
Enable (CE LOW) and Output Enable (OE) LOW while forcing
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then data from the memory location specified by the
address pins will appear on I/O0 to I/O7. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O8 to
I/O15. Refer to the truth table for a complete description of read
and write modes.
Logic Block Diagram
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
256K × 16
RAM Array
COLUMN DECODER
I/O0 – I/O7
I/O8 – I/O15
Power- Down
Circuit
BHE
BLE
BHE
WE
OE
BLE
CE
CE
Note:
1. For best practice recommendations, please refer to the CY application note System Design Guidelines on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05585 Rev. *F
Revised October 18, 2006
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Cypress Semiconductor Electronic Components Datasheet

CYK256K16MCCB Datasheet

4-Mbit (256K x 16) Pseudo Static RAM

No Preview Available !

CYK256K16MCCB pdf
Pin Configuration[2, 3, 4]
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CYK256K16MCCB
MoBL3™
VFBGA
Top View
12 3 4
56
BLE OE A0 A1 A2 NC
I/O8 BHE A3 A4 CE I/O0
I/O9 I/O10 A5 A6 I/O1 I/O2
VSS I/O11 A17 A7 I/O3 Vcc
VCC I/O12 DNU A16 I/O4 Vss
I/O14 I/O13 A14 A15 I/O5 I/O6
I/O15 NC A12 A13 WE I/O7
NC A8 A9 A10 A11 NC
A
B
C
D
E
F
G
H
Product Portfolio
Product
CYK256K16MCCB
VCC Range (V)
Min.
Typ.[5]
Max.
2.70 3.0 3.30
Speed
(ns)
55
60
70
Power Dissipation
Operating ICC(mA)
f = 1MHz
Typ.[5] Max.
f = fmax
Typ.[5] Max.
Standby ISB2(µA)
Typ.[5] Max.
1
5
14 22
17
40
8 15
Notes:
2. Ball H1, G2 and ball H6 for the VFBGA package can be used to upgrade to an 8-Mbit, 16-Mbit and 32-Mbit density, respectively.
3. NC “no connect” – not connected internally to the die.
4. DNU (Do Not Use) pins have to be left floating or tied to Vss to ensure proper application.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05585 Rev. *F
Page 2 of 10
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Part Number CYK256K16MCCB
Description 4-Mbit (256K x 16) Pseudo Static RAM
Maker Cypress Semiconductor
Total Page 10 Pages
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