http://www.www.datasheet4u.com

900,000+ Datasheet PDF Search and Download

Datasheet4U offers most rated semiconductors datasheets pdf




Cypress Semiconductor Electronic Components Datasheet

CYD09S72V Datasheet

(CYDxxS72V) FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM

No Preview Available !

CYD09S72V pdf
PRELIMINARY
CYD04S72V
CYD09S72V
CYD18S72V
FLEx72™ 3.3V 64K/128K/256K x 72
Synchronous Dual-Port RAM
Features
Functional Description
• True dual-ported memory cells that allow simultaneous
access of the same memory location
• Synchronous pipelined operation
• Family of 4-Mbit, 9-Mbit and 18-Mbit devices
• Pipelined output mode allows fast operation
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access
• 3.3V low power
— Active as low as 225 mA (typ)
— Standby as low as 55 mA (typ)
• Mailbox function for message passing
• Global master reset
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 484-ball FBGA (1 mm pitch)
• Counter wrap around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
• Counter readback on address lines
• Mask register readback on address lines
• Dual Chip Enables on both ports for easy depth
expansion
• Seamless Migration to Next Generation Dual Port
Family
The FLEx72 family includes 4-Mbit, 9-Mbit and 18-Mbit
pipelined, synchronous, true dual-port static RAMs that are
high-speed, low-power 3.3V CMOS. Two ports are provided,
permitting independent, simultaneous access to any location
in memory. The result of writing to the same location by more
than one port at the same time is undefined. Registers on
control, address, and data lines allow for minimal set-up and
hold time.
During a Read operation, data is registered for decreased
cycle time. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally (more details to follow). The internal write pulse width is
independent of the duration of the R/W input signal. The
internal write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CYD18S72V device have limited features. Please see
“Address Counter and Mask Register Operations[16]” on
page 6 for details.
Table 1. Product Selection Guide
Density
Part Number
Max. Speed (MHz)
Max. Access Time - clock to Data (ns)
Typical operating current (mA)
Package
Seamless Migration to Next Generation Dual Port Family
Cypress offers a migration path for all devices to the
next-generation devices in the Dual-Port family with a
compatible footprint. Please contact Cypress Sales for more
details
4-Mbit
(64K x 72)
CYD04S72V
167
4.0
225
484-ball FBGA
23mm x 23mm
9-Mbit
(128K x 72)
CYD09S72V
167
4.0
270
484-ball FBGA
23mm x 23mm
18-Mbit
(256K x 72)
CYD18S72V
133
5.0
410
484-ball FBGA
23mm x 23mm
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-06069 Rev. *D
Revised June 23, 2004


Cypress Semiconductor Electronic Components Datasheet

CYD09S72V Datasheet

(CYDxxS72V) FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM

No Preview Available !

CYD09S72V pdf
.
Logic Block Diagram[1]
FTSELL
PORTST[1:0]L
PRELIMINARY
CONFIG Block
CONFIG Block
DQ[71:0]L
BE [7:0]L
CE0L
CE1L
OEL
R/WL
IO
Control
IO
Control
CYD04S72V
CYD09S72V
CYD18S72V
FTSELR
PORTST[1:0]R
DQ [71:0]R
BE [7:0]R
CCEE01RR
OER
R/WR
Dual Ported Array
A [17:0]L
CNATD/MSLSKL
CNTENL
CNTRSTL
RETL
CNTINTL
CL
WRPL
INTL
BUSYL
Arbitration Logic
BUSYR
Address &
Counter Logic
Address &
Counter Logic
Mailboxes
INTR
READYL
LowSPDL
JTAG
RESET
LOGIC
A [17:0]R
CNCATND/TMSESRNKRR
CNTRSTR
RETR
CNCTIRNTR
WRPR
TRST
TMS
TDI
TDO
TCK
MRST
READYR
LowSPDR
Note:
1. CYD04S72V have 16 address bits, CYD09S72V have 17 address bits and CYD18S72V have 18 bits.
Document #: 38-06069 Rev. *D
Page 2 of 26


Part Number CYD09S72V
Description (CYDxxS72V) FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM
Maker Cypress Semiconductor
Total Page 26 Pages
PDF Download
CYD09S72V pdf
Download PDF File
CYD09S72V pdf
View for Mobile



Buy Electronic Components




Related Datasheet

1 CYD09S72V (CYDxxS72V) FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM Cypress Semiconductor
Cypress Semiconductor
CYD09S72V pdf
2 CYD09S72V18 Dual Port SRAM Cypress Semiconductor
Cypress Semiconductor
CYD09S72V18 pdf






Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

site map

webmaste! click here

contact us

Buy Components