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Cypress Semiconductor Electronic Components Datasheet

CY22701 Datasheet

1 PLL In-System Programmable Clock Generator

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CY22701 pdf
PRELIMINARY
CY22701
1 PLL In-System Programmable Clock Generator
Features
• In-system programmable through I2C Serial
Programming Interface (SPI)
• Programmable SRAM and non-volatile EEPROM
memory bits with 3.3V supply
• Integrated, phase-locked loop with programmable P
and Q counters, output dividers
• Low-jitter, high-accuracy outputs
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• 8-lead SOIC
Benefits
• Custom timing solutions for designs not suitable for
factory custom silicon, Xtals, or ASICs for production
• Program and optimize designs while chip is on system
board
• Programming voltages contained in chip
• High-performance PLL enables control of output
frequencies that are customizable to support a wide
range of applications
• Meets critical timing requirements in complex system
designs
• Meets industry-standard voltage platforms
• Industry standard packaging saves on board space
Part Number
CY22701
No. of Outputs
Input Frequency Range
Output Frequency Range
2 1 – 167 MHz (Driven Clock Input) {Commercial} 80 kHz – 200 MHz (3.3V) {Commercial}
1 –150 MHz (Driven Clock Input) {Industrial}
80 kHz –167 MHz (3.3V) {Industrial}
8 – 30 MHz (Crystal Reference) {Comm. or Ind.}
Logic Block Diagram
XIN
XOUT
[I2C- SPI:]
WP
SCL
SDAT
OSC
QΦ
VCO
P
PLL
Clock
Configuration
EEPROM
Memory Array
VDD VSS
OUTPUT
DIVIDERS
Output
Crosspoint
Switch
Array
CLK1
CLK2
Pin Configuration
XIN 1
VDD 2
SDA 3
VSS 4
8 XOUT
7 CLK2/WP
6 CLK1
5 SCL
8 PIN SOIC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07698 Rev. *B
Revised February 8, 2005


Cypress Semiconductor Electronic Components Datasheet

CY22701 Datasheet

1 PLL In-System Programmable Clock Generator

No Preview Available !

CY22701 pdf
PRELIMINARY
CY22701
Pin Description
Name
Pin Number
XIN 1
VDD
2
SDAT
3
VSS
4
SCL 5
CLK1
6
CLK2/WP
XOUT[1]
7
8
Description
Reference crystal input
3.3V voltage supply
Data input for serial programming
Ground
Clock signal input for serial programming
Clock output 1 (Default to reference frequency)
Clock output 2/Write Protect (Default Write Protect)
Reference crystal output
Functional Description
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EEPROM array along with on-chip
program the device for development,
or in production on the circuit board. An industry standard I2C
serial programming interface (SPI) is used to program the
scratchpad and clock core.
Clock Features
The programmable clock core is configured with the following
features:
Crystal Oscillator: Programmable drive and load, support
for external references up to 167 MHz. See Reference
Frequency (REF) on page 4
PLL: Programmable P, Q, offset, and loop filter parameters.
Outputs: 2 outputs and two programmable linear dividers.
The output swing of CLK1 and 2 is set by VDD (3.3V).
Clock configuration is stored in a dedicated 2-kbit block of
nonvolatile EEPROM and a 2-kbit block of volatile SRAM. The
SPI is used to write new configuration data to the on-chip
programmable registers that are defined within the clock
configuration memory blocks.
Serial Programming Interface (SPI)
The SPI uses industry-standard signaling in both standard and
fast modes to program the 2-kbit EEPROM dedicated to clock
configuration, and the 2-kbit SRAM block. See sections
beginning with Using the Serial Programming Interface on
page 2 for more information.
Default Start-up Condition for CY22701
The default clock configuration is:
• The crystal oscillator circuit is active.
• CLK1 outputs REF frequency.
• Pin 7 is configured as Write Protect (see “Write Protect (WP)
Registers” section on page 5 to configure as CLK2)
This default clock configuration is typically customized to meet
the needs of a specific application. It provides a clock signal
upon power-on, to facilitate in-system programming. Alterna-
tively, the CY22701 may be programmed with a different clock
configuration prior to placement of the CY22701 in systems.
While you can develop your own subroutine to program any or
all of the individual registers described in the following pages,
it may be easier to use CyberClocks™ to produce the required
register setting file.
Using the Serial Programming Interface
The CY22701 provides an industry-standard serial
programming interface for volatile and nonvolatile, in-system
programming of unique frequencies and options. Serial
programming and reprogramming allows for quick design
changes and product enhancements, eliminates inventory of
old design parts, and simplifies manufacturing.
The CY22701 is a group of two slave devices with addresses
as shown in Figure 1. The serial programming interface
address of the CY22701 clock configuration 2-kbit EEPROM
block is 68H. The serial programming interface address of the
CY22701 clock configuration 2-kbit SRAM block is 69H.
Should there be a conflict with any other devices in your
system, both device addresses can also be changed using
CyberClocks. Registers in the clock configuration 2-kbit SRAM
memory block are written, when the user wants to update the
clock configuration for on-the-fly changes. Registers in the
clock configuration EEPROM block are written, if the user
wants to update the clock configuration so that it is saved and
used again after power-up or reset.
All programmable registers in the CY22701 are addressed
with eight bits and contain eight bits of data. Table 1 lists the
specific register definitions and their allowable values. See
section Serial Programming Interface Timing on page 10, for
a detailed description.
clock config.
EE block
256 x 8 bits
Address:
1101000
clock config.
SRAM
256 x 8 bits
Address:
1101001
Figure 1. Device Addresses for EEPROM and SRAM Clock Configuration Blocks
Note:
1. Float XOUT if XIN is externally driven.
Document #: 38-07698 Rev. *B
Page 2 of 15


Part Number CY22701
Description 1 PLL In-System Programmable Clock Generator
Maker Cypress Semiconductor
Total Page 15 Pages
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