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Cypress Semiconductor Electronic Components Datasheet

CY14V104NA Datasheet

4-Mbit (512 K x 8 / 256 K x 16) nvSRAM

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CY14V104NA pdf
CY14V104LA
CY14V104NA
4-Mbit (512 K × 8 / 256 K × 16) nvSRAM
4-Mbit (512 K × 8 / 256 K × 16) nvSRAM
Features
Functional Description
25 ns and 45 ns access times
Internally organized as 512 K × 8 (CY14V104LA) or 256 K × 16
(CY14V104NA)
Hands off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
Infinite read, write, and recall cycles
1-million STORE cycles to QuantumTrap
The Cypress CY14V104LA/CY14V104NA is a fast static RAM,
with a non-volatile element in each memory cell. The memory is
organized as 512 K bytes of 8 bits each or 256 K words of 16 bits
each. The embedded non-volatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
non-volatile memory. The SRAM provides infinite read and write
cycles, while independent non-volatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
non-volatile elements (the STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM (the RECALL operation) from the non-volatile
memory. Both the STORE and RECALL operations are also
available under software control.
20 year data retention
Core VCC = 3.0 V to 3.6 V; IO VCCQ = 1.65 V to 1.95 V
Industrial temperature
48-ball fine-pitch ball grid array (FBGA) package
Pb-free and restriction of hazardous substances (RoHS)
compliance
Logic Block Diagram [1, 2, 3]
Quatrum Trap
VCC VCCQ VCAP
2048 X 2048
A0 R
POWER
A1 O
STORE
CONTROL
A2
A3
A4
A5
W
RECALL
D
E STATIC RAM
STORE/RECALL
CONTROL
HSB
A6 C ARRAY
A7
A8
A17
O 2048 X 2048
D
E
SOFTWARE
DETECT
A14 - A2
A18 R
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I
N
P
U
T
B COLUMN I/O
U
F
F
E
R COLUMN DEC
S
A9 A10 A11 A12 A13 A14 A15 A16
OE
WE
CE
BLE
BHE
Notes
1. Address A0–A18 for × 8 configuration and Address A0–A17 for × 16 configuration.
2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-53954 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 6, 2011
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Cypress Semiconductor Electronic Components Datasheet

CY14V104NA Datasheet

4-Mbit (512 K x 8 / 256 K x 16) nvSRAM

No Preview Available !

CY14V104NA pdf
CY14V104LA
CY14V104NA
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Read ....................................................................... 4
SRAM Write ....................................................................... 4
AutoStore Operation ........................................................ 4
Hardware STORE Operation ............................................ 4
Hardware RECALL (Power-Up) ....................................... 5
Software STORE ............................................................... 5
Software RECALL ............................................................. 5
Preventing AutoStore ....................................................... 6
Data Protection ................................................................. 6
Noise Considerations ....................................................... 6
Best Practices ................................................................... 7
Maximum Ratings ............................................................. 8
Operating Range ............................................................... 8
DC Electrical Characteristics .......................................... 8
Data Retention and Endurance ....................................... 9
Capacitance ...................................................................... 9
Thermal Resistance .......................................................... 9
AC Test Loads ................................................................ 10
AC Test Conditions ........................................................ 10
AC Switching Characteristics ....................................... 11
SRAM Read Cycle .................................................... 11
SRAM Write Cycle ..................................................... 11
Switching Waveforms .................................................... 11
AutoStore/Power-Up RECALL ....................................... 14
Switching Waveforms .................................................... 14
Software Controlled STORE/RECALL Cycle ................ 15
Switching Waveforms .................................................... 15
Hardware STORE Cycle ................................................. 16
Switching Waveforms .................................................... 16
Truth Table For SRAM Operations ................................ 17
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC Solutions ......................................................... 22
Document #: 001-53954 Rev. *F
Page 2 of 22
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Cypress Semiconductor Electronic Components Datasheet

CY14V104NA Datasheet

4-Mbit (512 K x 8 / 256 K x 16) nvSRAM

No Preview Available !

CY14V104NA pdf
CY14V104LA
CY14V104NA
Pinouts
1
(× 8)
Top View
(not to scale)
2 34 5
Figure 1. Pin Diagram – 48-ball FBGA
(× 16)
Top View
(not to scale)
6 12 34 5
6
NC OE A0 A1 A2 VCC
NC NC A3 A4 CE NC
DQ0 NC A5
A6 NC DQ4
VSS DQ1 A17 A7 DQ5 VCCQ
VCCQ DQ2 VCAP A16 DQ6 VSS
DQ3 NC A14 A15 NC DQ7
NC HSB A12 A13 WE NC
A18 A8 A9 A10 A11 NC [4]
A
B
C
D
E
F
G
H
BLE OE A0 A1 A2 VCC
DQ8 BHE A3
A4 CE DQ0
DQ9 DQ10 A5
A6 DQ1 DQ2
VSS DQ11 A17 A7 DQ3 VCCQ
VCCQ DQ12 VCAP A16 DQ4 VSS
DQ14 DQ13 A14 A15 DQ5 DQ6
DQ15 HSB A12 A13 WE DQ7
NC[4] A8 A9 A10 A11 NC
A
B
C
D
E
F
G
H
Pin Definitions
Pin Name I/O Type
Description
A0–A18 Input
A0–A17
DQ0–DQ7 Input/output
DQ0–DQ15
WE Input
Address Inputs Used to Select One of the 524,288 bytes of the nvSRAM for × 8 Configuration.
Address Inputs Used to Select One of the 262,144 words of the nvSRAM for × 16 Configuration.
Bidirectional Data I/O Lines for × 8 Configuration. Used as input or output lines depending on operation.
Bidirectional Data I/O Lines for × 16 Configuration. Used as input or output lines depending on operation.
Write Enable Input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
CE Input
OE Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
I/O pins are tri-stated on deasserting OE HIGH.
BHE
BLE
VSS
VCC
VCCQ
HSB
Input
Input
Ground
Byte High Enable, Active LOW. Controls DQ15–DQ8.
Byte Low Enable, Active LOW. Controls DQ7–DQ0.
Ground for the Device. Must be connected to the ground of the system.
Power supply Power Supply Inputs to the Core of the Device.
Power supply Power Supply Inputs for the Inputs and Outputs of the Device.
Input/output
Hardware Store Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a non-volatile STORE operation. After each Hardware
and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection
optional).
VCAP Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
non-volatile elements.
NC No Connect No Connect. This pin is not connected to the die.
Note
4. Address expansion for 8-Mbit. NC pin not connected to die.
Document #: 001-53954 Rev. *F
Page 3 of 22
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Part Number CY14V104NA
Description 4-Mbit (512 K x 8 / 256 K x 16) nvSRAM
Maker Cypress Semiconductor
Total Page 22 Pages
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