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Cypress Semiconductor Electronic Components Datasheet

CY14E256L Datasheet

256-Kbit (32K x 8) nvSRAM

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CY14E256L pdf
PRELIMINARY
CY14E256L
256-Kbit (32K x 8) nvSRAM
Features
• 25 ns and 45 ns Access Times
• “Hands-off” Automatic STORE on Power Down with
external 68µF capacitor
STORE to QuantumTrap® Nonvolatile Elements is
initiated by Software, Hardware or Autostore® on
www.DataSheet4UP.coowmer-down
RECALL to SRAM Initiated by Software or Power-up
• Infinite READ, WRITE and RECALL Cycles
• 15 mA Typical ICC at 200 ns Cycle Time
• 1,000,000 STORE Cycles to QuantumTrap
• 100-Year Data Retention to QuantumTrap
• Single 5V Operation +10%
• Commercial Temperature
• SOIC Package
• RoHS Compliance
Functional Description
The Cypress CY14E256L is a fast static RAM with a nonvol-
atile element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
Infinite read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down.
On power-up, data is restored to the SRAM (the RECALL
operation) from the nonvolatile memory. Both the STORE and
RECALL operations are also available under software control.
A hardware STORE may be initiated with HSB pin.
Logic Block Diagram
Quantum Trap
VCC
VCAP
512 X 512
A5
STORE
POWER
CONTROL
A6
A7
A8
A9
A 11
A 12
STATIC RAM
ARRAY
512 X 512
RECALL
STORE/
RECALL
CONTROL
HSB
A 13
A14 SOFTWARE
-DETECT
A13 A0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709
• 408-943-2600
Document #: 001-06968 Rev. *C
Revised November 28, 2006
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Cypress Semiconductor Electronic Components Datasheet

CY14E256L Datasheet

256-Kbit (32K x 8) nvSRAM

No Preview Available !

CY14E256L pdf
Pin Configurations
PRELIMINARY
CY14E256L
www.DataSheet4U.com
V CAP
A 14
A 12
A7
A6
A5
A4
A3
NC
A2
A1
A0
DQ0
DQ1
DQ2
V SS
1 32
2 31
3 30
4 29
5 28
6 27
7 32 - Lead SOIC 26
8 25
9
Top View
24
10
(Not To Scale)
23
11 22
12 21
13 20
14 19
15 18
16 17
V CC
HSB
WE
A 13
A8
A9
A11
OE
NC
A 10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
Pin Definitions
Pin Name I/O Type
Description
A0–A14
Input Address Inputs used to select one of the 32,768 bytes of the nvSRAM.
DQ0-DQ7 Input/Output Bidirectional Data I/O lines. Used as input or output lines depending on operation.
WE Input Write Enable Input, active LOW. When selected LOW, enables data on the I/O pins to be written to
the address location latched by the falling edge of CE.
CE Input Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE Input Output Enable, active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the I/O pins to tri-state.
VSS
VCC
HSB
VCAP
Ground Ground for the device. Should be connected to ground of the system.
Power Supply Power Supply inputs to the device.
Input/Output Hardware Store Busy. When low this output indicates a Hardware Store is in progress. When pulled
low external to the chip it will initiate a nonvolatile STORE operation. A weak internal pull-up resistor
keeps this pin high if not connected. (Connection Optional)
Power Supply Autostore® Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
NC No Connect No Connects. This pin is not connected to the die.
Document #: 001-06968 Rev. *C
Page 2 of 16
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Part Number CY14E256L
Description 256-Kbit (32K x 8) nvSRAM
Maker Cypress Semiconductor
Total Page 16 Pages
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