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Cypress Semiconductor Electronic Components Datasheet

CY14C256Q Datasheet

256-Kbit (32 K x 8) SPI nvSRAM

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CY14C256Q pdf
CY14C256Q
CY14B256Q
CY14E256Q
256-Kbit (32 K × 8) SPI nvSRAM
256-Kbit (32 K × 8) SPI nvSRAM
Features
256-Kbit nonvolatile static random access memory (nvSRAM)
internally organized as 32 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using SPI
instruction (Software STORE) or HSB pin (Hardware
STORE)
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
Support automatic STORE on power-down with a small
capacitor (except for CY14X256Q1A)
High reliability
Infinite read, write, and RECALL cycles
1million STORE cycles to QuantumTrap
Data retention: 20 years at 85 C
40 MHz and 104 MHz High speed serial peripheral interface
(SPI)
40 MHz clock rate SPI write and read with zero cycle delay
104 MHz clock rate SPI write and SPI read (with special fast
read instructions)
Supports SPI mode 0 (0,0) and mode 3 (1,1)
SPI access to special functions
Nonvolatile STORE/RECALL
8-byte serial number
Manufacturer ID and Product ID
Sleep mode
Write protection
Hardware protection using Write Protect (WP) pin
Software protection using Write Disable instruction
Software block protection for 1/4, 1/2, or entire array
Low power consumption
Average active current of 3 mA at 40 MHz operation
Average standby mode current of 150 A
Sleep mode current of 8 A
Logic Block Diagram
VCC VCAP
Industry standard configurations
Operating voltages:
• CY14C256Q: VCC = 2.4 V to 2.6 V
• CY14B256Q: VCC = 2.7 V to 3.6 V
• CY14E256Q: VCC = 4.5 V to 5.5 V
Industrial temperature
8- and 16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Functional Overview
The Cypress CY14X256Q combines a 256-Kbit nvSRAM[1] with
a nonvolatile element in each memory cell with serial SPI
interface. The memory is organized as 32 K words of 8 bits each.
The embedded nonvolatile elements incorporate the
QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile elements (STORE operation) takes place
automatically at power-down (except for CY14X256Q1A). On
power-up, data is restored to the SRAM from the nonvolatile
memory (RECALL operation). You can also initiate the STORE
and RECALL operations through SPI instruction.
For a complete list of related documentation, click here.
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14X256Q1A CY14X256Q2A CY14X256Q3A
No Yes Yes
Yes Yes Yes
No No Yes
Serial Number
8x8
SI
CS
SCK
WP
SO
Power Control
Block
SLEEP
SPI Control Logic
Write Protection
Instruction decoder
Manufacturer ID /
Product ID
RDSN/WRSN/RDID
READ/WRITE
STORE/RECALL/ASENB/ASDISB
Memory
Data &
Address
Control
QuantumTrap
32 K x 8
SRAM
32 K x 8
STORE
RECALL
WRSR/RDSR/WREN
Status Register
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-65282 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 12, 2014



Cypress Semiconductor Electronic Components Datasheet

CY14C256Q Datasheet

256-Kbit (32 K x 8) SPI nvSRAM

No Preview Available !

CY14C256Q pdf
CY14C256Q
CY14B256Q
CY14E256Q
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Write ................................................................. 4
SRAM Read ................................................................ 4
STORE Operation ....................................................... 4
AutoStore Operation .................................................... 5
Software STORE Operation ........................................ 5
Hardware STORE and HSB pin Operation ................. 5
RECALL Operation ...................................................... 5
Hardware RECALL (Power-Up) .................................. 5
Software RECALL ....................................................... 5
Disabling and Enabling AutoStore ............................... 6
Serial Peripheral Interface ............................................... 6
SPI Overview ............................................................... 6
SPI Modes ................................................................... 7
SPI Operating Features .................................................... 8
Power-Up .................................................................... 8
Power-Down ................................................................ 8
Active Power and Standby Power Modes ................... 8
SPI Functional Description .............................................. 9
Status Register ............................................................... 10
Read Status Register (RDSR) Instruction ................. 10
Fast Read Status Register
(FAST_RDSR) Instruction ................................................ 10
Write Status Register (WRSR) Instruction ................ 10
Write Protection and Block Protection ......................... 12
Write Enable (WREN) Instruction .............................. 12
Write Disable (WRDI) Instruction .............................. 12
Block Protection ........................................................ 12
Hardware Write Protection (WP) ............................... 12
Memory Access .............................................................. 13
Read Sequence (READ) Instruction .......................... 13
Fast Read Sequence (FAST_READ) Instruction ...... 13
Write Sequence (WRITE) Instruction ........................ 13
nvSRAM Special Instructions ........................................ 15
Software STORE (STORE) Instruction ..................... 15
Software RECALL (RECALL) Instruction .................. 15
AutoStore Enable (ASENB) Instruction ..................... 15
AutoStore Disable (ASDISB) Instruction ................... 15
Special Instructions ....................................................... 16
SLEEP Instruction ..................................................... 16
Serial Number ................................................................. 16
WRSN (Serial Number Write) Instruction .................. 16
RDSN (Serial Number Read) Instruction ................... 17
FAST_RDSN
(Fast Serial Number Read) Instruction ............................. 17
Device ID ......................................................................... 18
RDID (Device ID Read) Instruction ........................... 18
FAST_RDID (Fast Device ID Read) Instruction ........ 19
HOLD Pin Operation ................................................. 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
DC Electrical Characteristics ........................................ 20
Data Retention and Endurance ..................................... 21
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 22
AC Test Conditions ........................................................ 22
AC Switching Characteristics ....................................... 23
Switching Waveforms .................................................... 24
AutoStore or Power-Up RECALL .................................. 25
Switching Waveforms .................................................... 25
Software Controlled STORE and RECALL Cycles ...... 26
Switching Waveforms .................................................... 26
Hardware STORE Cycle ................................................. 27
Switching Waveforms .................................................... 27
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Package Diagrams .......................................................... 29
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC® Solutions ...................................................... 33
Cypress Developer Community ................................. 33
Technical Support ..................................................... 33
Document Number: 001-65282 Rev. *I
Page 2 of 33



Cypress Semiconductor Electronic Components Datasheet

CY14C256Q Datasheet

256-Kbit (32 K x 8) SPI nvSRAM

No Preview Available !

CY14C256Q pdf
CY14C256Q
CY14B256Q
CY14E256Q
Pinouts
CS
SO
WP
VSS
18
2 CY14X256Q1A 7
3
Top View
not to scale
6
45
Figure 1. 8-pin SOIC pinout [2, 3, 4]
VCC
HOLD
SCK
SI
CS
SO
VCAP
VSS
18
2 CY14X256Q2A 7
3
Top View
not to scale
6
45
VCC
HOLD
SCK
SI
Figure 2. 16-pin SOIC pinout
NC
NC
NC
NC
WP
HOLD
NC
VSS
1 16
2 15
3 CY14X256Q3A 14
Top View
4 not to scale 13
5 12
6 11
7 10
89
VCC
NC
VCAP
SO
SI
SCK
CS
HSB
Pin Definitions
Pin Name [2, 3, 4] I/O Type
Description
CS Input Chip Select. Activates the device when pulled LOW. Driving this pin high puts the device in low
power standby mode.
SCK
Input
Serial
of this
Clock. Runs
clock. Serial
at speeds up to
output is driven
a
at
maximum
the falling
oefdfgSeCKo.f
Serial input
the clock.
is
latched
at
the
rising
edge
SI Input Serial Input. Pin for input of all SPI instructions and data.
SO Output Serial Output. Pin for output of data through SPI.
WP Input Write Protect. Implements hardware write protection in SPI.
HOLD
Input HOLD Pin. Suspends serial operation.
HSB
Input/Output Hardware STORE Busy:
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB
a weak internal
is driven HIGH
pull-up resistor
for a short
keeps this
ptiimneH(ItGHHHH(DE)xwteirtnhasltpaunldl-aurpdroeustisptuotrhciognhnceucrtrieonntoapntdiotnhael)n.
Input: Hardware STORE implemented by pulling this pin LOW externally.
VCAP
Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It
must never be connected to ground.
NC No connect No Connect: This pin is not connected to the die.
VSS Power supply Ground
VCC Power supply Power supply
Notes
2. HSB pin is not available in 8-pin SOIC packages (CY14X256Q1A/CY14X256Q2A).
3. CY14X256Q1A part does not have VCAP pin and does not support AutoStore.
4. CY14X256Q2A part does not have WP pin.
Document Number: 001-65282 Rev. *I
Page 3 of 33




Part Number CY14C256Q
Description 256-Kbit (32 K x 8) SPI nvSRAM
Maker Cypress Semiconductor
Total Page 30 Pages
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