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Cypress Semiconductor Electronic Components Datasheet

CB664 Datasheet

I2C Clock Distribution Buffer

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CB664
I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM
Approved Product
Product Features
7 output buffer for high clock fanout applications.
Output may be individually disabled with I2C
VDD = 3.3 volts
Output frequency range 10 MHz to 100 MHz
<250ps skew between output clocks.
16-pin SSOP and TSSOP package.
Block Diagram
SDATA
SCLK
REFIN
I2C Control
VDD
2
1
2
2
SDR(0:1)
SDR2
SDR(3:4)
SDR(5:6)
Product Description
The device is a high fanout system clock buffer. Its
primary application is to distribute clocks needed to
support a wide range of applications such as SDRAM
clocks. This device provides low skew distribution
clock heavily loaded. One important application of
this component is where long traces are used to
transport clocks from their generating devices to their
loads. The creation of EMI and the degradation of
waveform rise and fall times is greatly reduces by
running a single reference clock trace to this device
and then using it to these devices EMI is therefore
minimized and board real estate is saved.
Pin Configuration
VDD
SDR0
SDR1
VSS
CLKIN
SDR2
VDD
SDATA
1
2
3
4
5
6
7
8
16 SDR6
15 SDR5
14 VSS
13 VDD
12 SDR4
11 SDR3
10 VSS
9 SCLK
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07024 Rev. **
5/6/99
Page 1 of 8


Cypress Semiconductor Electronic Components Datasheet

CB664 Datasheet

I2C Clock Distribution Buffer

No Preview Available !

CB664 pdf
www.DataSheet4U.com
CB664
I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM
Approved Product
Pin Description
Pin No.
5
2,3,6,11,12,15,16
8
9
4,10,14
1,7,13
Pin Name
CLKIN
SDR(0:6)
SDATA
SCLK
VSS
VDD
PWR
VDD
VDD
-
I/O
I
O
I/O
-I
--
--
Type
PAD
BUF1
PAD
PAD
-
-
Description
This pin is connected to the input reference clock.
This clock be in the range of 10.0 to 100.0 MHz
Low Skew output clock.
Serial data of I2C-wire control interface. Has internal
pull-up resistor.
Serial data of I2C-wire control interface. Has internal
pull-up resistor
COMMON Ground
Power for output clock buffers and core logic
Maximum Ratings
Maximum Input Voltage Relative to VSS: VSS – 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
0o to +125oC
Operating Temperature:
0o to +70oC
Maximum Power Supply:
7V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07024 Rev. **
5/6/99
Page 2 of 8


Part Number CB664
Description I2C Clock Distribution Buffer
Maker Cypress Semiconductor
Total Page 8 Pages
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