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6 Hits
• 4Mb x 36 and 8Mb x 18 organizations available • Organized as a single logical memory bank • 933 MHz maximum operating frequency • 933 MT/s peak tran...
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6 Hits
• On-Chip ECC with virtually zero SER • Configurable Read Latency (3.0 or 2.0 cycles) • Simultaneous Read and Write SigmaDDR-IIIe™ Interface • Common ...
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5 Hits
• FT pin for user-configurable flow through or pipeline operation
• Single Cycle Deselect (SCD) operation • 1.8 V +10%/–10% core power supply • 1.8 V ...
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5 Hits
• 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O supply • Intergrated data comparator for Tag RAM application • FT mode pin for flow through or ...
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5 Hits
• 4Mb x 36 and 8Mb x 18 organizations available • Organized as a single logical memory bank • 933 MHz maximum operating frequency • 933 MT/s peak tran...