AT89C51 Datasheet | Specifications & PDF Download

Features • Compatible with MCS-51™ Products • 4K Bytes of In-System Reprogrammable Flash Memory – Endurance: 1,000 Write/Erase Cycles • Fully Static O

(53 views)

Features • 80C52X2 Core (6 Clocks per Instruction) – Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode – Dual Data Pointer – Full-duplex Enh

(49 views)

Features • 80C51 Core Architecture • 256 Bytes of On-chip RAM • 256 Bytes of On-chip XRAM • 16K Bytes of On-chip Flash Memory – Data Retention: 10 Yea

(44 views)

Features • 80C51 Core Architecture • 256 Bytes of On-chip RAM • 256 Bytes of On-chip XRAM • 16K Bytes of On-chip Flash Memory – Data Retention: 10 Yea

(42 views)

Features • Programmable Audio Output for Interfacing with Common Audio DAC – PCM Format Compatible – I2S Format Compatible • 8-bit MCU C51 Core-based

(40 views)

Features www.DataSheet4U.com • Protocol – USB Used as Physical Layer – Device Firmware Upgrade Class Compliant – USB Clock Auto-Configuration • In-Sy

(38 views)

Features • 80C52X2 Core (6 Clocks per Instruction) – Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode – Dual Data Pointer – Full-duplex Enh

(37 views)

Features • 80C52X2 Core (6 Clocks per Instruction) – Maximum Core Frequency 48 MHz in X1 Mode, 24MHz in X2 Mode – Dual Data Pointer – Full-duplex Enha

(34 views)

Features • 80C52 Compatible – 8051 Instruction Compatible – Six 8-bit I/O Ports (64 pins or 68 Pins Versions) – Four 8-bit I/O Ports (44 Pins Version)

(34 views)

AT89C51RD2 / AT89C51ED2 QualPack Qualification Package AT89C51ED2 FLASH 8-bit C51 Microcontroller 64 Kbytes FLASH, 2 Kbytes EEPROM AT89C51RD2 / AT8

(34 views)

Features • 80C51 Core – 12 or 6 Clocks per Instruction (X1 and X2 Modes) – 256 Bytes Scratchpad RAM – Dual Data Pointer – Two 16-bit Timer/Counters: T

(34 views)

Features • 80C52X2 Core (6 Clocks per Instruction) – Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode – Dual Data Pointer – Full-duplex Enh

(33 views)

Features • Protocol – USB Used as a Physical Layer – Device Firmware Upgrade Class Compliant – Auto-Frequency Detection • In-System Programming – Read

(32 views)

Features • MPEG I/II-Layer 3 Hardwired Decoder – Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency – Separated Digital Volu

(32 views)

Features • 80C52 Compatible – 8051 Pin and Instruction Compatible – Four 8-bit I/O Ports – Three 16-bit Timer/Counters – 256 Bytes Scratch Pad RAM – 9

(31 views)

Features • 80C52 Compatible – 8051 Pin and Instruction Compatible – Four 8-bit I/O Ports – Three 16-bit Timer/Counters – 256 Bytes Scratch Pad RAM – 9

(30 views)

Features • MPEG I/II-Layer 3 Hardwired Decoder – Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency – Separated Digital Volu

(29 views)

Features • 80C52X2 Core (6 Clocks per Instruction) – Maximum Core Frequency 48 MHz in X1 Mode, 24MHz in X2 Mode – Dual Data Pointer – Full-duplex Enha

(29 views)

Features • 80C52 Compatible – 8051 Instruction Compatible – Four 8-bit I/O Ports (44 Pins Version) – Three 16-bit Timer/Counters – 256 bytes Scratch P

(29 views)

Features • 80C51 Core : – 6 Clocks per Instruction – Speed up to 16 MHz • 768 Bytes RAM • AT83C5122: 32 Kbytes ROM • AT83C5123: 30 Kbytes ROM • AT85C5

(28 views)