| No |
Part Number |
Description |
Manufacture |
PDF |
| 103 |
54ACT00 |
Quad 2-Input NAND Gate
54AC00/54ACT00 Quad 2-Input NAND Gate
July 2003
54AC00/54ACT00 Quad 2-Input NAND Gate
General Description
The ’AC/’ACT00 contains four 2-input NAND gates. n Standard Microci |
National Semiconductor
|
|
| 102 |
54ACT109 |
Dual JK Positive Edge-Triggered Flip-Flop
54AC109 • 54ACT109 Dual JK Positive Edge-Triggered Flip-Flop
August 1998
54AC109 • 54ACT109 Dual JK Positive Edge-Triggered Flip-Flop
General Description
The ’AC/’ACT109 |
National Semiconductor
|
|
| 101 |
54ACT11000 |
Quadruple 2-Input Positive-NAND Gates (Rev. A)
|
ETCTI
|
|
| 100 |
54ACT11002 |
Quadruple 2-Input Positive-NOR Gates (Rev. A)
|
ETCTI
|
|
| 99 |
54ACT11010 |
Triple 3-Input Positive-NAND Gates
ą
• Inputs Are TTL-Voltage Compatible • Flow-Through Architecture to Optimize
PCB Layout
• Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
• EPICt (Enhanced-Perform |
etcTI
|
|
| 98 |
54ACT11011 |
TRIPLE 3-INPUT POSITIVE-AND GATES
54ACT11011, 74ACT11011 TRIPLE 3-INPUT POSITIVE-AND GATES
• Inputs Are TTL-Voltage Compatible • Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin VCC and GND Configurations
Minimize Hi |
etcTI
|
|
| 97 |
54ACT11021 |
DUAL 4-INPUT POSITIVE-AND GATES
• Inputs Are TTL-Voltage Compatible • Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
• EPICt (Enhanced-Performance I |
etcTI
|
|
| 96 |
54ACT11030 |
8-Input Positive-NAND Gates
|
ETCTI
|
|
| 95 |
54ACT11034 |
Hex Noninverters
ą
• Inputs Are TTL-Voltage Compatible • Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
• EPICt (Enhanced-Performan |
etcTI
|
|
| 94 |
54ACT11109 |
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993
• Inputs Are TTL-Voltage Compatible • Flow-Through Archit |
etcTI
|
|
| 93 |
54ACT11138 |
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
54ACT11138, 74ACT11138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A – D3266, JANUARY 1989 – REVISED APRIL 1993
• Designed Specifically for High-Speed
54ACT11138 . . . J PACKAGE
Memory D |
etcTI
|
|
| 92 |
54ACT112 |
Dual JK Negative Edge-Triggered Flip-Flop
54ACT112 Dual JK Negative Edge-Triggered Flip-Flop
September 1998
54ACT112 Dual JK Negative Edge-Triggered Flip-Flop
General Description
The ’ACT112 contains two independent, |
National Semiconductor
|
|
