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74HCT594-Q100 - 8-bit shift register

This page provides the datasheet information for the 74HCT594-Q100, a member of the 74HC594-Q100 8-bit shift register family.

Description

The 74HC594-Q100; 74HCT594-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).

The 74HC594-Q100; 74HCT594-Q100 is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from 40 C to +85 C and from 40 C to +125 C.
  • Synchronous serial input and output.
  • Complies with JEDEC standard No.7A.
  • 8-bit parallel output.
  • Shift and storage registers have independent direct clear and clocks.
  • Independent clocks for shift and storage registers.
  • 100 MHz (typical).
  • ESD protection:.
  • MIL-STD-883, method 3015 exceeds 2000 V.
  • HBM JESD22-A114F.

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Datasheet preview – 74HCT594-Q100

Datasheet Details

Part number 74HCT594-Q100
Manufacturer nexperia
File Size 867.70 KB
Description 8-bit shift register
Datasheet download datasheet 74HCT594-Q100 Datasheet
Additional preview pages of the 74HCT594-Q100 datasheet.

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Full PDF Text Transcription

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74HC594-Q100; 74HCT594-Q100 8-bit shift register with output register Rev. 2 — 13 June 2016 Product data sheet 1. General description The 74HC594-Q100; 74HCT594-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC594-Q100; 74HCT594-Q100 is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct overriding clears (SHR and STR) are provided on both the shift and storage registers. A serial output (Q7S) is provided for cascading purposes. Both the shift and storage register clocks are positive-edge triggered. If both clocks are connected together, the shift register is always one count pulse ahead of the storage register.
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