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74HCT390D - Dual decade ripple counter

Download the 74HCT390D datasheet PDF. This datasheet also covers the 74HC390 variant, as both devices belong to the same dual decade ripple counter family and are provided as variant models within a single manufacturer datasheet.

Description

The 74HC390; 74HCT390 is a dual 4-bit decade ripple counter divided into four separately clocked sections.

The counters have two divide-by-2 sections and two divide-by-5 sections.

Features

  • Input levels:.
  • For 74HC390: CMOS level.
  • For 74HCT390: TTL level.
  • Two BCD decade or bi-quinary counters.
  • One device can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100.
  • Two master reset inputs to clear each decade counter individually.
  • Supply voltage range from 4.5 V to 5.5 V.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standard JESD7A.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC390-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HCT390D
Manufacturer Nexperia
File Size 253.04 KB
Description Dual decade ripple counter
Datasheet download datasheet 74HCT390D Datasheet

📁 Similar Datasheet

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74HCT390 Dual decade ripple counter Philips
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74HCT30 8-Input NAND Gate Texas Instruments
74HCT30 8-Input NAND Gate NXP

Other Datasheets by Nexperia

Part Number Description
74HCT390 Dual decade ripple counter
74HCT393 Dual 4-bit binary ripple counter
74HCT393-Q100 Dual 4-bit binary ripple counter
74HCT393BQ Dual 4-bit binary ripple counter
74HCT393D Dual 4-bit binary ripple counter

Full PDF Text Transcription

Click to expand full text
74HC390; 74HCT390 Dual decade ripple counter Rev. 5 — 18 October 2021 Product data sheet 1. General description The 74HC390; 74HCT390 is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections share an asynchronous master reset input (nMR) and can be used in a BCD decade or bi-quinary configuration. If master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clocks (nCP0 and nCP1) of each section allow ripple counter or frequency division applications of divide-by-2, 4, 5, 10, 20, 25, 50 or 100.
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