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74HC280D - 9-bit odd/even parity generator/checker

Download the 74HC280D datasheet PDF. This datasheet also covers the 74HC280 variant, as both devices belong to the same 9-bit odd/even parity generator/checker family and are provided as variant models within a single manufacturer datasheet.

Description

The 74HC280; 74HCT280 is a 9-bit parity generator or checker.

Both even and odd parity outputs are available.

The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH.

Features

  • Word-length easily expanded by cascading.
  • Generates either odd or even parity for nine data bits.
  • Wide supply voltage range from 2.0 to 6.0 V.
  • Input levels:.
  • For 74HC280: CMOS level.
  • For 74HCT280: TTL level.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC280-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HC280D
Manufacturer Nexperia
File Size 240.32 KB
Description 9-bit odd/even parity generator/checker
Datasheet download datasheet 74HC280D Datasheet

📁 Similar Datasheet

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74HC21 DUAL 4-INPUT AND GATE STMicroelectronics
74HC21D Dual 4-Input AND Gate Toshiba

Other Datasheets by Nexperia

Part Number Description
74HC280 9-bit odd/even parity generator/checker
74HC20 Dual 4-input NAND gate
74HC20-Q100 Dual 4-input NAND gate
74HC20D Dual 4-input NAND gate
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Full PDF Text Transcription

Click to expand full text
74HC280; 74HCT280 9-bit odd/even parity generator/checker Rev. 4 — 16 August 2021 Product data sheet 1. General description The 74HC280; 74HCT280 is a 9-bit parity generator or checker. Both even and odd parity outputs are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs are HIGH. Expansion to larger word sizes is accomplished by tying the even outputs (PE) of up to nine parallel devices to the final stage data inputs. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2.
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