Datasheet4U Logo Datasheet4U.com

74AUP1G3208 - Low-power 3-input OR-AND gate

General Description

The 74AUP1G3208 is a single 3-input OR-AND gate.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

Key Features

  • Wide supply voltage range from 0.8 V to 3.6 V.
  • High noise immunity.
  • Complies with JEDEC standards:.
  • JESD8-12 (0.8 V to 1.3 V).
  • JESD8-11 (0.9 V to 1.65 V).
  • JESD8-7 (1.65 V to 1.95 V).
  • JESD8-5 (2.3 V to 2.7 V).
  • JESD8C (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM JESD22-A114F Class 3A exceeds 5000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • CDM JESD22-C101E exceeds 1000 V.
  • Low static power consump.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74AUP1G3208 Low Power 3-Input OR-AND Gate NXP

Other Datasheets by Nexperia

Part Number Description
74AUP1G32 Low-power 2-input OR-gate
74AUP1G32-Q100 Low-power 2-input OR-gate
74AUP1G332 Low-power 3-input OR-gate
74AUP1G34 Low-power buffer
74AUP1G34-Q100 Low-power buffer
74AUP1G373 Low-power D-type transparent latch
74AUP1G373-Q100 Low-power D-type transparent latch
74AUP1G374 Low-power D-type flip-flop
74AUP1G374-Q100 Low-power D-type flip-flop
74AUP1G38 Low-power 2-input NAND gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74AUP1G3208 Low-power 3-input OR-AND gate Rev. 10 — 9 May 2023 Product data sheet 1. General description The 74AUP1G3208 is a single 3-input OR-AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • Wide supply voltage range from 0.8 V to 3.6 V • High noise immunity • Complies with JEDEC standards: • JESD8-12 (0.8 V to 1.3 V) • JESD8-11 (0.9 V to 1.65 V) • JESD8-7 (1.65 V to 1.