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74ALVC74D - Dual D-type flip-flop

Download the 74ALVC74D datasheet PDF. This datasheet also covers the 74ALVC74 variant, as both devices belong to the same dual d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

Description

The 74ALVC74 is a dual positive edge triggered, D-type flip-flop.

It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.

The set and reset are asynchronous active LOW inputs that operate independently of the clock input.

Features

  • Wide supply voltage range from 1.65 V to 3.6 V.
  • Complies with JEDEC standard:.
  • JESD8-7 (1.65 to 1.95 V).
  • JESD8-5 (2.3 to 2.7 V).
  • JESD8B (2.7 to 3.6 V).
  • 3.6 V tolerant inputs/outputs.
  • CMOS low power consumption.
  • Direct interface with TTL levels (2.7 V to 3.6 V).
  • Power-down mode.
  • Latch-up performance exceeds 250 mA.
  • ESD protection:.
  • HBM JESD22-A114E exceeds 2000 V.
  • MM JESD22-A115-A.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74ALVC74-nexperia.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Nexperia

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74ALVC74 Dual D-type flip-flop
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Full PDF Text Transcription

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74ALVC74 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 6 — 27 July 2021 Product data sheet 1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2.
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