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74AHC377PW - Octal D-type flip-flop

Download the 74AHC377PW datasheet PDF. This datasheet also covers the 74AHC377 variant, as both devices belong to the same octal d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

Description

The 74AHC377; 74AHCT377 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

It is specified in compliance with JEDEC standard No.

7-A.

Features

  • I Balanced propagation delays I All inputs have Schmitt-trigger actions I Inputs accept voltages higher than VCC I Ideal for addressable register.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC377-nexperia.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Nexperia

Part Number Description
74AHC377 Octal D-type flip-flop
74AHC377-Q100 Octal D-type flip-flop
74AHC377D Octal D-type flip-flop
74AHC373 Octal D-type transparant latch
74AHC374 Octal D-type flip-flop

Full PDF Text Transcription

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74AHC377; 74AHCT377 Octal D-type flip-flop with data enable; positive-edge trigger Rev. 02 — 12 June 2008 Product data sheet 1. General description The 74AHC377; 74AHCT377 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC377; 74AHCT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock input (CP) loads all flip-flops simultaneously when the data enable input (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. The E input is only required to be stable one set-up time prior to the LOW-to-HIGH transition for predictable operation.
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