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D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 14 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Contain Six Flip-Flops With Single-Rail
Outputs
D Applications Include:
− Buffer/Storage Registers − Shift Registers − Pattern Generators
description/ordering information
These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK.
SNJ54HC174J Datasheet
