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SN74SSTV32852 - 24-BIT TO 48-BIT REGISTERED BUFFER

Datasheet Summary

Description

This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET) input.

All outputs are SSTL_2, Class II compatible.

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Datasheet preview – SN74SSTV32852

Datasheet Details

Part number SN74SSTV32852
Manufacturer Texas Instruments
File Size 418.76 KB
Description 24-BIT TO 48-BIT REGISTERED BUFFER
Datasheet download datasheet SN74SSTV32852 Datasheet
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D Member of the Texas Instruments Widebus Family D 1-to-2 Outputs Support Stacked DDR DIMMs D Supports SSTL_2 Data Inputs D Outputs Meet SSTL_2 Class II Specifications D Differential Clock (CLK and CLK) Inputs D Supports LVCMOS Switching Levels on the RESET Input SN74SSTV32852 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES361C – AUGUST 2001 – REVISED FEBRUARY 2003 D RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low D Pinout Optimizes DIMM PCB Layout D One Device Per DIMM Required D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) description/ordering information This 24-bit to 48-bit registered buffer
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