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SN74SSTV32852-EP - 24-Bit To 48-Bit Registered Buffer

Datasheet Summary

Description

This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET) input.

All outputs are SSTL_2, Class II compatible.

Features

  • 1.
  • 2 Controlled Baseline.
  • One Assembly/Test Site, One Fabrication Site.
  • Extended Temperature Performance of.
  • 40°C to 85°C.
  • Enhanced Diminishing Manufacturing Sources (DMS) Support.
  • Enhanced Product-Change Notification.
  • Qualification Pedigree (1).
  • Member of the Texas Instruments Widebus™ Family.
  • 1-to-2 Outputs Support Stacked DDR DIMMs (1) Component qualification in accordance with JEDEC and industry standards to ensur.

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Datasheet preview – SN74SSTV32852-EP

Datasheet Details

Part number SN74SSTV32852-EP
Manufacturer Texas Instruments
File Size 360.89 KB
Description 24-Bit To 48-Bit Registered Buffer
Datasheet download datasheet SN74SSTV32852-EP Datasheet
Additional preview pages of the SN74SSTV32852-EP datasheet.

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Full PDF Text Transcription

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www.ti.com SN74SSTV32852-EP 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES700 – OCTOBER 2007 FEATURES 1 •2 Controlled Baseline – One Assembly/Test Site, One Fabrication Site • Extended Temperature Performance of –40°C to 85°C • Enhanced Diminishing Manufacturing Sources (DMS) Support • Enhanced Product-Change Notification • Qualification Pedigree (1) • Member of the Texas Instruments Widebus™ Family • 1-to-2 Outputs Support Stacked DDR DIMMs (1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
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