Datasheet4U Logo Datasheet4U.com

SN74SSTV16859 - 13-BIT TO 26-BIT REGISTERED BUFFER

Datasheet Summary

Description

This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET) input.

All outputs are SSTL_2, Class II compatible.

📥 Download Datasheet

Datasheet preview – SN74SSTV16859

Datasheet Details

Part number SN74SSTV16859
Manufacturer Texas Instruments
File Size 961.73 KB
Description 13-BIT TO 26-BIT REGISTERED BUFFER
Datasheet download datasheet SN74SSTV16859 Datasheet
Additional preview pages of the SN74SSTV16859 datasheet.

📁 Similar Datasheet

  • SN74S1051 - 12-BIT SCHOTTKY BARRIER DIODE BUS TERMINATOR (California Micro Devices)
  • SN74S1051R - 12-BIT SCHOTTKY BARRIER DIODE BUS TERMINATOR (California Micro Devices)
  • SN74S1051T - 12-BIT SCHOTTKY BARRIER DIODE BUS TERMINATOR (California Micro Devices)
  • SN74S350 - 4 Bit Shifter (AMD)
  • SN74S557 - (SN74S557 / SN74S558) 8x8 High Speed Schottky Multipliers (Monolithic Memories)
  • SN74S558 - (SN74S557 / SN74S558) 8x8 High Speed Schottky Multipliers (Monolithic Memories)
  • SN74S74N - Dual D-Type Flip-Flop (ETC)
  • SN74101 - AND-OR Gate (ETC)
  • SN74102 - AND Gate (ETC)
  • SN74103 - Dual J-K Flip-Flop (ETC)
Other Datasheets by Texas Instruments

Full PDF Text Transcription

Click to expand full text
D Member of the Texas Instruments Widebus Family D 1-to-2 Outputs to Support Stacked DDR DIMMs D Supports SSTL_2 Data Inputs D Outputs Meet SSTL_2 Class II Specifications D Differential Clock (CLK and CLK) Inputs D Supports LVCMOS Switching Levels on the RESET Input D RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low D Pinout Optimizes DIMM PCB Layout D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) description/ordering information This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.
Published: |